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ksz80 91mnx / ksz8091rnb 10base - t/100base - tx physical layer transceiver revision 1. 2 linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com august 31, 20 1 5 revision 1. 2 general description the ksz80 9 1 is a single - supply 10base - t/100base - tx ethernet physical - layer transceiver for transmission and reception of data over standard cat - 5 unshielded twisted pair (utp) cable. the ksz80 9 1 is a highly - integrated phy solution. it r educes board cost and simplifies board layout by using on - chip termination resistors for the differential pairs , by integrating a low - noise regulator to supply the 1.2v core , and by offering a flexible 1.8/2.5/3.3v digital i/o interface. the ksz80 9 1mnx off ers the media independent interface (mii) and the ksz80 9 1rnb offers the reduced media independent interface (rmii) for direct connection with mii/rmii - compliant ethernet mac processors and switches. energy efficient ethernet (eee) provides further power sa ving during idle traffic periods and wake - on- lan (wol) provides a mechanism for the ksz8091 to wake up a system that is in standby power mode. the ksz80 9 1 provides diagnostic features to facilitate system bring - up and debugging in production testing and in product deployment. parametric nand tree support enables fault detection between ksz80 9 1 i/os and the board. micrel linkmd ? tdr - based cable diagnostics identify faulty copper cabling. the ksz80 9 1mnx and ksz80 9 1rnb are available in 32 - pin, lead - free qfn pa ckages (see ? ordering information ?). datasheets and support documentation are available on website at: www.micrel.com . features ? single - chip 10base - t/100base - tx ieee 802.3 compliant ethernet transceiver ? mii interface support (ksz8091mnx) ? rmii v1.2 in terface support with a 50mhz reference clock output to mac, and an option to input a 50mhz reference clock (ksz8091rnb) ? back - to - back mode support for a 100mbps copper repeater ? mdc/mdio management interface for phy register configuration ? programmable interrupt output ? led outputs for link and activity status indication, plus speed indication for ksz8091rnb ? on - chip termination resistors for the differential pairs ? baseline wander correction ? hp auto mdi/mdi - x to reliably detect and correct straight - through and crossover cable connections with disable and enable option ? auto - negotiation to automatically select the highest link - up speed (10/100mbps) and duplex (half/full) ? energy efficient ethernet (eee) support with low - power idle (lpi) mode and clock stoppage (mii version only) for 100base - tx and transmit amplitude reduction with 10base - te option ? wake - on- lan (wol) support with either magic packet, link status change, or robust custom - packet detection ? hbm esd rating (6 k v) function al diagram
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 2 revision 1. 2 features (continued) ? power - down and power - saving modes ? linkmd tdr - based cable diagnostics to identify faulty copper cabling ? parametric nand tree support for fault detection between chip i/os and the board ? loopback modes for diagnostics ? singl e 3.3v power supply with vdd i/o options for 1.8v, 2.5v, or 3.3v ? built - in 1.2v regulator for core ? available in 32 - pin (5mm 5mm) qfn package applications ? game console ? ip phone ? ip set - top box ? ip tv ? lom ? printer ordering information part number tempera ture range package lead finish description ksz80 9 1mnxca 0c to + 70c 32- pin qfn pb - free mii, eee and wol support, commercial temperature . ksz80 9 1mnxia ( 1 ) ? 40c to + 85c 32- pin qfn pb - free mii, eee and wol support, industrial temperature . ksz80 9 1rnbca 0 c to + 70c 32- pin qfn pb - free rmii with 25mhz crystal/clock input and 50mhz rmii ref_clk output (power - up default), eee and wol support, commercial temperature . ksz80 9 1rnbia ( 1 ) ? 40c to + 85c 32- pin qfn pb - free rmii with 25mhz crystal/clock input and 50m hz rmii ref_c lk output (power - up default), eee and wol support, industrial temperature . ksz80 9 1mnx -eval ksz80 9 1mnx evaluation board (mounted with ksz80 9 1mnx device in commercial temperature) ksz80 9 1rnb -eval ksz80 9 1rnb evaluation board (mounted with ksz80 9 1rnb device in commercial temperature) note: 1. contact factory for lead time .
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 3 revision 1. 2 revision history revision date summary of changes 1.0 7/2 / 20 13 new datasheet. 1.1 12/8 /14 added silver wire bonding part numbers to order information. updated orderin g information to include ordering part number and device marking. 1.2 8/ 31 /15 add max frequency for mdc in mii management (miim) interface section. updated ordering information table. updated descriptions for figure 27. a dd a note for figure 28. updat ed descriptions in local loopback section for data loopback path. updated table 20 and table 2 4 . add a note for table 26. updated description and add an equation in linkmd section. add hbm esd rating in features.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 4 revision 1. 2 contents list of figures .......................................................................................................................................................................... 6 list of tables ........................................................................................................................................................................... 7 pin configuration ? ksz8091mnx ......................................................................................................................................... 8 pin description ? ksz8091mnx ............................................................................................................................................. 8 strapping options ? ksz8091mnx ...................................................................................................................................... 12 pin configuration ? ksz8091rnb ........................................................................................................................................ 13 pin description ? ksz8091rn b ........................................................................................................................................... 13 strapping options ? ksz8091rnb ....................................................................................................................................... 17 functional description: 10base - t/100base - tx transceiver ................................................................................................ 18 100base - tx transmit ........................................................................................................................................................ 18 100base - tx receive ......................................................................................................................................................... 1 8 scrambler/de - scrambler (100base - tx only) ................................................................................................................... 18 10base - t transmit ............................................................................................................................................................ 18 10base - t receive ............................................................................................................................................................. 19 sqe and jabber function (10b ase - t only) ...................................................................................................................... 19 pll clock synthesizer ...................................................................................................................................................... 19 auto - negotiation ................................................................................................................................................................ 19 mii data interface (ksz8091mnx only) ............................................................................................................................... 21 mii signal definition ........................................................................................................................................................... 21 mii signal diagram ............................................................................................................................................................ 23 rmii data interface (ksz8091rnb only) ............................................................................................................................. 24 rmii ? 25mhz clock mode ................................................................................................................................................ 24 rmii ? 50mhz clock mode ................................................................................................................................................ 24 rmii signal definition ........................................................................................................................................................ 24 rmii signal diagram ......................................................................................................................................................... 25 back - to - back mode ? 100mbps c opper repeater ............................................................................................................... 27 mii back - to - back mode (ksz8091mnx only) ................................................................................................................... 27 rmii back - to - back mode (ksz8091rnb only) ................................................................................................................. 28 mii management (miim) interface ......................................................................................................................................... 29 interrupt (intrp) ................................................................................................................................................................... 29 hp auto mdi/mdi - x .............................................................................................................................................................. 30 straight cable .................................................................................................................................................................... 30 crossover cable ................................................................................................................................................................ 31 loopback mode ..................................................................................................................................................................... 32 local (digital) loopback .................................................................................................................................................... 32 remote (analog) loopback ............................................................................................................................................... 33 linkmd ? cable diagnostic .................................................................................................................................................... 34 nand tree support .............................................................................................................................................................. 35 nand tree i/o testing ..................................................................................................................................................... 36 power management .............................................................................................................................................................. 37 power - saving mode .......................................................................................................................................................... 37 energy - detect power - down mode .................................................................................................................................... 37 power - do wn mode ............................................................................................................................................................ 37 slow - oscillator mode ......................................................................................................................................................... 37
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 5 revision 1. 2 energy efficient ethernet (eee) ............................................................................................................................................ 38 transmit direction control (mac - to - phy) ........................................................................................................................ 39 receive direction control (phy - to - mac) ......................................................................................................................... 40 registers associated with eee ......................................................................................................................................... 41 wake - on - lan ....................................................................................................................................................................... 42 magic - packet detection ..................................................................................................................................................... 42 customized - packet detection ........................................................................................................................................... 43 link status change detection ........................................................................................................................................... 43 reference circuit for power and ground connections ......................................................................................................... 44 typical current/power consumption .................................................................................................................................... 45 transceiver (3.3v), digital i/os (3.3v) .............................................................................................................................. 45 transceiver (3.3v), di gital i/os (2.5v) .............................................................................................................................. 45 transceiver (3.3v), digital i/os (1.8v) .............................................................................................................................. 46 register map ......................................................................................................................................................................... 47 standard registers ............................................................................................................................................................... 49 ieee - defined registers ? descriptions ............................................................................................................................. 49 vendor - specific registers ? descriptions ......................................................................................................................... 54 mmd registers ...................................................................................................................................................................... 60 mmd registers ? descriptions .......................................................................................................................................... 61 absolute maximum rat ings .................................................................................................................................................. 66 operating ratings ................................................................................................................................................................. 66 electrical characteristics ....................................................................................................................................................... 66 timin g diagrams ................................................................................................................................................................... 68 mii sqe timing (10base - t) .............................................................................................................................................. 68 mii transmit timing (10base - t) ........................................................................................................................................ 69 mii receive timing (10base - t) ......................................................................................................................................... 70 mii transmit timing (100base - tx) ................................................................................................................................... 71 mii receive timing (100base - tx) .................................................................................................................................... 72 rmii timing ....................................................................................................................................................................... 73 auto - negotiation timing .................................................................................................................................................... 74 mdc/mdio timing ............................................................................................................................................................ 75 power - up/reset timing .................................................................................................................................................... 76 reset circuit .......................................................................................................................................................................... 77 reference circuits ? led strap - in pi ns ................................................................................................................................ 78 reference clock ? connection and selection ...................................................................................................................... 79 magnetic ? connection and selection .................................................................................................................................. 80 package information ............................................................................................................................................................. 82
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 6 revision 1. 2 list of figures figure 1. auto - negotiation flow chart ................................................................................................................................. 20 figure 2. ksz8091mnx mii interface .................................................................................................................................. 23 figure 3. ksz8091rnb rmii interface (25mhz clock mode) ............................................................................................. 26 figure 4. ksz8091rnb rmii interface (50mhz clock mode) ............................................................................................. 26 figure 5. ksz8091mnx/rnb to ksz8091mnx/rnb back - to - back copper repeater ...................................................... 27 figure 6. typical straight cable connection ....................................................................................................................... 30 figure 7. typical crossover cable connection ................................................................................................................... 31 figure 8. local (dig ital) loopback ....................................................................................................................................... 32 figure 9. remote (analog) loopback .................................................................................................................................. 33 figure 10. lpi mode (refresh transmissions and quiet periods) ...................................................................................... 38 figure 11. lpi transition ? mii (100mbps) transmit ........................................................................................................... 39 figure 12. lpi transition ? rmii (100mbps) transmit ......................................................................................................... 39 figure 13. lpi transition ? mii (100mbps) receive ............................................................................................................ 40 figure 14. lpi transition ? rmii (100mbps) receive .......................................................................................................... 40 figure 15. ksz8091mnx/rnb power and ground connections ........................................................................................ 44 figure 16. mii sqe timing (10base - t) ............................................................................................................................... 68 figur e 17. mii transmit timing (10base - t) ......................................................................................................................... 69 figure 18. mii receive timing (10base - t) .......................................................................................................................... 70 figure 19. mii transmit timing (100base - t x) ..................................................................................................................... 71 figure 20. mii receive timing (100base - tx) ...................................................................................................................... 72 figure 21. rmii timing ? data received from rmii ............................................................................................................ 73 figure 22. rmii timing ? data input to rmii ....................................................................................................................... 73 figure 23. auto - negotiation fast link pulse (flp) timing ................................................................................................. 74 figure 24. mdc/mdio timing .............................................................................................................................................. 75 figure 25. power - up/reset timing ...................................................................................................................................... 76 figure 26. recommended reset circuit .............................................................................................................................. 77 figure 27. recommended reset circuit for interfacing with cpu/fpga reset output ..................................................... 77 figure 28. reference circuits for led s trapping pins ......................................................................................................... 78 figure 29. 25mhz crystal/oscillator reference clock connection ..................................................................................... 79 figure 30. 50mhz oscillator reference clock connection ................................................................................................. 79 figure 31. typical magnetic interface circuit ....................................................................................................................... 80
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 7 revision 1. 2 list of tables table 1. mii signal definition ............................................................................................................................................... 21 table 2. rmii signal definition ............................................................................................................................................. 24 table 3. mii signal connection for mii back - to - back mode (100base - tx copper repeater) ............................................ 27 table 4. rmii signal connection for rmii back - to - back mode (100base - tx copper repeater) ...................................... 28 table 5. mii management frame format for the ksz8091mnx/rnb ................................................................................ 29 table 6. mdi/mdi - x pin definition ....................................................................................................................................... 30 table 7. nand tree test pin order for ksz8091mnx ....................................................................................................... 35 table 8. nand tree test pin order for ksz8091rnb ....................................................................................................... 36 table 9. ksz8091mnx/rnb power pin description ........................................................................................................... 44 table 10. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 3.3v) .......................................................... 45 table 11. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 2.5v) .......................................................... 45 table 12. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 1.8v) .......................................................... 46 table 13. s tandard registers supported by ksz8091mnx/rnb ....................................................................................... 47 table 14. mmd registers supported by ksz8091mnx/rnb ............................................................................................. 48 table 15. portal regis ters (access to indirect mmd registers) .......................................................................................... 60 table 16. mii sqe timing (10base - t) parameters ............................................................................................................. 68 table 17. mii transmit timing (10 base - t) parameters ...................................................................................................... 69 table 18. mii receive timing (10base - t) parameters ........................................................................................................ 70 table 19. mii transmit timing (100base - tx) paramet ers .................................................................................................. 71 table 20. mii receive timing (100base - tx) parameters ................................................................................................... 72 table 21. rmii timing parameters ? ksz8091rnb (25mhz input to x i pin, 50mhz output from ref_clk pin) ............. 73 table 22. rmii timing parameters ? ksz8091rnb (50mhz input to xi pin) ..................................................................... 73 table 23. au to - negotiation fast link pulse (flp) timing parameters ............................................................................... 74 table 24. mdc/mdio timing parameters ........................................................................................................................... 75 table 25. power - up/reset tim ing parameters ................................................................................................................... 76 table 26. 25mhz crystal / reference clock selection criteria ........................................................................................... 79 table 27. 50mhz oscillator / reference clock selection criteria ....................................................................................... 7 9 table 28. magnetics selection criteria ................................................................................................................................ 81 table 29. compatible single - port 10/100 magnetics ........................................................................................................... 81
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 8 revision 1. 2 pin configuration ? ksz8091mnx 32- pin (5mm 5mm) qfn
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 9 revision 1. 2 pin description ? ksz8091mnx pin number pin name type ( 2 ) pin function 1 gnd gnd ground 2 vdd_1.2 p 1.2v core v dd (power sup plied by ksz80 9 1mnx) decouple with 2.2f and 0.1f capacitors to ground. 3 vdda_3.3 p 3.3v analog v dd 4 rxm i/o physical receive or transmit signal ( ? differential) 5 rxp i/o physical receive or transmit signal (+ differential) 6 txm i/o physical trans mit or receive signal ( ? differential) 7 txp i/o physical transmit or receive signal (+ differential) 8 xo o crystal feedback for 25mhz crystal this pin is a no connect if an oscillator or external clock source is used. 9 xi i crystal/oscillator/ externa l clock input 25mhz 50ppm 10 rext i set phy transmit output current connect a 6.49k resistor to ground on this pin. 11 mdio ipu/opu management interface (mii) data i/o this pin has a weak pull - up, is open- drain , and requires an external 1.0k pull - up resistor. 12 mdc ipu management interface (mii) clock input this clock pin is synchronous to the mdio data pin. 13 rxd3/ phyad0 ipu/o mii mode: mii receive data output[3] ( 3 ) config mode: the pull - up/pull - down value i s latched as phyaddr[0] at the de- assertion of reset. see the ? strapping options ? ksz8091mnx ? section for details. notes: 2. p = power supply. gnd = ground. i = input. o = output. i/o = bi - directional. ipu = input with internal pull - up (see ? electrical characteristics ? for value). ipd = input with internal pull - down (see ? electrical characteristics ? for value). ipu/o = input with internal pull - up (see ? electrical characteristics ? for value) during power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (see ? electrical characteristics ? for value) during power - up/reset; output pin otherwise. ipu/opu = input with internal pull - up (see ? electrical characteristics ? for value) and output with internal pull - up (see ? electrical characteristics ? for value). 3. mii rx mode: the rxd[3:0] bits are synchronous with rxc. when rxdv is asserted, rxd[3:0] presents valid data to the mac. 4. mii tx mode: the txd[3:0] bits are synchronous with txc. when txen is asserted, txd[3:0] presents valid data from the mac.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 10 revision 1. 2 pin description ? ksz8091mnx (continued) pin number pin name type ( 2 ) pin function 14 rxd2/ phyad1 ipd/o mii mode: mii receive data outpu t[2] ( 3 ) config mode: the pull - up/pull - down value is lat ched as phyaddr[1] at the de assertion of reset. see the ? strapping options ? ksz8091mnx ? section for details. 15 rxd1/ phyad2 ipd/o mii mode: mii receive data output[1] ( 3 ) config mode: the pull - up/pull - down value i s latched as phyaddr[2] at the de- assertion of reset. see the ? strapping options ? ksz8091mnx ? section for details. 16 rxd0/ duplex ipu/o mii mode: mii receive data output[0] ( 3 ) config mode: the pull - up/pull - down valu e is latched as duplex at the de- assertion of reset. see the ? strapping options ? ksz8091mnx ? section for details. 17 vddio p 3.3v, 2.5v, or 1.8v digital v dd 18 rxdv/ config2 ipd/o mii mode: mii receive data valid output config mode: the pull - up/pull - down valu e is latched as config2 at the de - assertion of reset. see the ? strapping options ? ksz8091mnx ? section for details. 19 rxc/ b- cast_off ipd/o mii mode: mii receive clock output config mode: the pull - up/pull - down value is latched as b - cast_off at the de- assertion of reset. see the ? strapping options ? ksz8091mnx ? section for details. 20 rxer/ iso ipd/o mii mode: mii receive error output config mode: the pull - up/pull - down valu e is latched as isolate at the de - assertion of reset. see the ? strapping options ? ksz8091mnx ? section for details. 21 intrp/ pme_n2/ nand_tree# ipu/opu interrupt output: programmable interrupt output, with re gister 1bh as the interrupt control/status register, for programming the interrupt conditions a nd reading the interru pt status. register 1fh, bit [9] sets the interrupt output to active low (default) or active high. pme_n output: programmable pme_n output (pin option 2). when asserted low, this pin signals that a wol event has occurred. config mode: the pull - up/pull - down value is latched as nand tree# at the dea ssertion of reset. see the ? strapping options ? ksz8091 mnx ? section for details. this pin has a weak pull - up and is an open- drain . for interrupt (when active low) and pme functions, this pin requires an external 1.0k pull - up resistor to vddio ( digital v dd ). 22 txc / pme_en ipd /o mii mode: mii transmit clock output mii back -to - back mode: mii transmit clock input config mode: the pull - up/pull - down value is latched as pme_en at the de- assertion of reset. see the ? strapping options ? ksz8091mnx ? section for details. 23 txen i mii mode: mii transmit enable input
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 11 revision 1. 2 pin description ? ksz8091mnx (continued) pin number pin name type ( 2 ) pin function 24 txd0 i mii mode: mii transmit data input[0] ( 4 ) 25 txd1 i mii mode: mii transmit data input[1] ( 4 ) 26 txd2 i mii mode: mii transmit data input[2] ( 4 ) 27 txd3 i mii mode: mii transmit data input[3] ( 4 ) 28 col/ config0 ipd/o mii mode: mii collision detect output config mode: the pull - up/pull - down valu e is latched as config0 at the de - assertion of reset. see the ? stra pping options ? ksz8091mnx ? section for details. 29 crs/ config1 ipd/o mii mode: mii carrier sense output config mode: the pull - up/pull - down valu e is latched as config1 at the de - assertion of reset. see the ? str apping options ? ksz8091mnx ? section for details. 30 led0/ pme_n1/ nwayen ipu/o led output: programmable led0 output pme_n output: programmable pme_n output (pin option 1) in this mode, this pin has a weak pull - up, is an open - drain, and requires an ex ternal 1.0 k ? pull - up resistor to vddio ( digital v dd ). config mode: latch ed as auto - negotiation enable (r egister 0h, bit [ 12 ]) at the de - assertion of reset. see the ? strapping options ? ksz8091mnx ? section for deta ils. the led0 pin is programmable u sing r egister 1fh bits [5:4], and is defined as follows. led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definiti on no link high off link low on led mode = [10], [11] reserved 31 txer ip d mii mode: mii transmit error input for eee mode, this pin is driven by the eee - mac to put the ksz8091mnx transmit into the lpi state. for non - eee mode, this pin is not define d for error transmission from mac to ksz8091mnx and can be left as a no connect. 32 rst# ipu chip reset (active low) paddle gnd gnd ground
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 12 revision 1. 2 strapping options ? ksz80 9 1mnx pin number pin name type ( 5 ) pin func tion 15 14 13 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o phyad[2:0] is latched at de - assertion of reset and is configurable to any value from 0 to 7 with phy address 1 as the default value. phy address 0 is assigned by default as the broadcast phy address, bu t it can be assigned as a unique phy address after pulling the b - cast_off strappin g pin high or writing a ?1? to r egister 16h, bit [9]. phy address bits [4:3] are set to 00 by default. 18 29 28 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] str ap - in pins are latched at the de- assertion of reset. config[2:0] mode 000 mii (default) 110 mii back -to - back 001? 101, 111 reserved ? not used 22 pme_en ipd/o pme output for wake -on - lan pull - up = enable pull - down (default) = disable at the de - asser tion of reset, this pin value is latched into r egister 16h, bit [15 ]. 20 iso ipd/o isolate mode pull - up = enable pull - down (default) = disable at the de - assertion of reset, this pin value is latched into r egister 0h, bit [10]. 16 duplex ipu/o duplex mo de pull - up (default) = half - duplex pull - down = full - duplex at the de - assertion of reset, this pin value is latched into r egister 0h, bit [8]. 30 nwayen ipu/o nway auto - negotiation enable pull - up (default) = enable auto - negotiation pull - down = disable auto - negotiation at the de - assertion of reset, this pin value is latched into r egister 0h, bit [12]. 19 b- cast_off ipd/o broadcast off ? for phy address 0 pull - up = phy address 0 is set as an unique phy address pull - down (default) = phy address 0 is set as a broadcast phy address at the de - assertion of reset, this pin value is latched by the chip. 21 nand_tree# ipu/opu nand tree mode pull - up (default) = disable pull - down = enable at the de - assertion of reset, this pin value is latched by the chip. no te: 5. ipu/o = input with internal pull - up (see ? electrical characteristics ? for value) during power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (see ? electrical characteristics ? for value) during power - up/reset; output pin otherwise. ipu/opu = input with internal pull - up (see ? electrical characteristics ? for value) and output with internal pull - up (see ? electrical characteristics ? for value). the strap - in pins are latched at the de - assertion of reset. in some systems, the mac mii receive input pins may drive high/low during power - up or reset, and conseq uently cause the phy strap - in pins on the mii signals to be latched to unintended high/low states. in this case, external pull - ups (4.7k ? ) or pull - downs (1.0k ? ) should be added on these phy strap - in pins to ensure that the intended values are strapped - in correctly.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 13 revision 1. 2 pin configuration ? ksz8091rnb 32- pin (5mm 5mm) qfn
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 14 revision 1. 2 pin description ? ksz8091rnb pin number pin name type ( 6 ) pin function 1 gnd gnd ground 2 vdd_1.2 p 1.2v core v dd (power supplied by ksz80 9 1 rnb ) decouple with 2.2f and 0.1f capacitors to ground. 3 vdda_3.3 p 3.3v analog v dd 4 rxm i/o physical receive or transmit signal ( ? differential) 5 rxp i/o physical receive or transmit signal (+ differential) 6 txm i/o physical transmit or receive signal ( ? differential) 7 txp i/o physical transmit or receive signal (+ differential) 8 xo o crystal feedback for 25mhz crystal this p in is a no connect if an oscillator or external clock source is used. 9 xi i 25m hz mode: 25mhz 50ppm crystal/ oscillator/external clock input 50mhz mode: 50mhz 50ppm oscillator/ external clock input 10 rext i set phy transmit output current connect a 6 .49k resistor to ground on this pin. 11 mdio ipu/opu management interface (mii) data i/o this pin has a weak pull - up, is open- drain , and requires an external 1.0k pull - up resistor. 12 mdc ipu management interface (mii) clock input this clock pin is sy nchronous to the mdio data pin. 13 phyad0 ipu/o the pull - up/pull - down value is latched as phyaddr[0] at the de- assertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. notes: 6. p = power s upply. gnd = ground. i = input. o = output. i/o = bi - directional. ipu = input with internal pull - up (see ? electrical characteristics ? for value). ipu/o = input with internal pull - up (see ? electrical characteristics ? for value) during power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (see ? electrical characteristics ? for value) during power - up/res et; output pin otherwise. ipu/opu = input with internal pull - up (see ? electrical characteristics ? for value) and output with internal pull - up (see ? electrical characteristics ? for value). nc = pin is not bonded to the die. 7. rmii rx mode: the rxd[1:0] bits are synchronous with the 50mhz rmii reference clock. for each clock period in which crs_dv is asserted, two bits of recovered data are sent by the phy to the mac. 8. r mii tx mode: the txd[1:0] bits are synchronous with the 50mhz rmii reference clock. for each clock period in which txen is as serted, two bits of data are received by the phy from the mac.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 15 revision 1. 2 pin description ? ksz8091rnb (continued) pin number pin name type ( 6 ) pin function 14 phyad1 ipd/o the pull - up/pull - down value is latched as phyaddr[1] at the de- assertion of reset . see the ? strapping options ? ksz8091rnb ? section for details. 15 rxd1/ phyad2 ipd/o r mii mode: r mii receive data output[1] ( 7 ) config mode: the pull - up/pull - down value i s latched as phyaddr[2] at the deassertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. 16 rxd0/ duplex ipu/o r mii mode: r mii receive data output[0] ( 7 ) config mode: the pull - up/pull - down value is latched as duplex at the de - assertio n of reset. see the ? strapping options ? ksz8091rnb ? section for details. 17 vddio p 3.3v, 2.5v, or 1.8v digital v dd 18 crs_ dv/ config2 ipd/o r mii mode: rmii carrier sense/receive data valid output config mode: the pull - up/pull - down valu e is latched as config2 at the deassertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. 19 ref_clk / b- cast_off ipd/o r mii mode: 25mhz mode: this pin provides t he 50mhz rmii reference clock output to the mac. see also xi (pin 9). 50mhz mode: this pin is a no connect. see also xi (pin 9). config mode: the pull - up/pull - down value is latched as b - cast_off at the de- assertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. 20 rxer/ iso ipd/o r mii mode: r mii receive error output config mode: the pull - up/pull - down valu e is latched as isolate at the deassertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. 21 intrp/ pme_n2/ nand_tree# ipu/opu interrupt output: programmable interrupt output, with register 1bh as the interrupt control/status register, for programming t he interrupt conditions a nd reading the interru pt status. register 1fh, bit [9] sets the interrupt output to active low (default) or active high. pme_n output: programmable pme_n output (pin option 2). when asserted low, this pin signals that a wol event h as occurred. config mode: the pull - up/pull - down value is latched as nand tree# at the de- assertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. this pin has a weak pull - up and is an open- drain . for interrupt (when active low) and pme functions, this pin requires an external 1.0k pull - up resistor to vddio ( digital v dd ). 22 pme_en ipd /o the pull - up/pull - down value is latched as pme_en at the de- assertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. 23 txen i rmii transmit enable input 24 txd0 i rmii transmit data input[0] ( 8 ) 25 txd1 i rmii transmit data input[1] ( 8 ) 26 nc nc no connect ? this pin is not bonded and can be left floating.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 16 revision 1. 2 pin description ? ksz8091rnb (continued) pin number pin name type ( 6 ) pin function 27 nc nc no connec t ? this pin is not bonded and can be left floating. 28 config0 ipd/o the pull - up/pull - down valu e is latched as config0 at the de - assertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. 29 config1 ipd/o the pull - up/pull - down valu e is latched as config1 at the de - assertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. 30 led0/ pme_n1/ nwayen ipu/o led output: programm able led0 output pme_n output: programmable pme_n output (pin option 1). in this mode, this pin has a weak pull - up, is an open- drain, and requires an external 1.0k? pull - up resistor to vddio ( digital v dd ). config mode: latched as auto - negotiation enable (r egister 0h, bit [12]) at the deassertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. the le d0 pin is programmable using r egister 1fh bits [5 :4], and is defined as follows. led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definition no link high off link low on led mode = [10], [11] reserved 31 led1/ speed ipu/o led output: prog rammable led1 output config mode: latched as speed (r egister 0h, bit [ 13 ]) at the de- assertion of reset. see the ? strapping options ? ksz8091rnb ? section for details. the led 1 pin is programmable using r egister 1f h bits [5 :4], and is defined as follows. led mode = [00] speed pin state led definition 10base -t high off 100base -tx low on led mode = [01] activity pin state led definition no activity high off activity toggle blinking led mode = [10], [11] reserved 32 rst# ipu chip reset (active low) paddle gnd gnd ground
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 17 revision 1. 2 strapping options ? ksz80 9 1rnb pin number pin name type ( 6 ) pin function 15 14 13 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o phyad[2:0] is lat ched at de - assertion of reset and is configurable to any value from 0 to 7 with phy address 1 as the default value. phy address 0 is assigned by default as the broadcast phy address, but it can be assigned as a unique phy address after pulling the b - cast_o ff strappin g pin high or writing a ?1? to r egister 16h, bit [9]. phy address bits [4:3] are set to 00 by default. 18 29 28 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap - in pins are latched at the de- assertion of reset. config[2:0] mode 001 rmii 1 01 rmii back - to - back 000, 010 ? 100, 110, 111 reserved ? not used 22 pme_en ipd/o pme output for wake -on - lan pull - up = enable pull - down (default) = disable at the de - assertion of reset, this pin value is latched into r egister 16h, bit [15 ]. 20 iso ipd/o isolate mode pull - up = enable pull - down (default) = disable at the de - assertion of reset, this pin value is latched into register 0h, bit [10]. 31 speed ipu/o speed mode pull - up (default) = 1 00mbps pull - down = 10mbps at the de - assertion of re set, this pin value is latched into r egister 0h, bit [13] as the speed se lect, and also is latched into r egister 4h (auto - negotiation advertisement) as the speed capability support. 16 duplex ipu/o duplex mode pull - up (default) = half - duplex pull - down = f ull - duplex at the de - assertion of reset, this pin value is latched into r egister 0h, bit [8]. 30 nwayen ipu/o nway auto - negotiation enable pull - up (def ault) = enable auto - negotiation pull - down = disable auto- negotiation at the de - assertion of reset, this pin value is latched into r egister 0h, bit [12]. 19 b- cast_off ipd/o broadcast off ? for phy address 0 pull - up = phy address 0 is set as an unique phy address pull - down (default) = phy address 0 is set as a broadcast phy address at the de - assertion of res et, this pin value is latched by the chip. 21 nand_tree# ipu/opu nand tree mode pull - up (default) = disable pull - down = enable at the de - assertion of reset, this pin value is latched by the chip. the strap - in pins are latched at the de - assertion of reset . in some systems, the mac r mii receive input pins may drive high/low during power - up or reset, and consequently cause the phy strap- in pins on the r mii signals to be latched to unintended high/low states. in this case, external pull - ups (4.7k ? ) or pull - downs (1.0k ? ) should be added on these phy strap - in pins to ensure that the intended values are strapped - in correctly.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 18 revision 1. 2 functional description : 10base - t/100base - tx transceiver the ksz80 9 1 is an integrated single 3.3v supply fast ethernet transce iver. it is fully compliant with the ieee 802.3 specification, and reduces board cost and simplifies board layout by using on - chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2v core. on the copper media side, the ksz80 9 1 supports 10base - t and 100base - tx for transmission and reception of data over a standard cat - 5 unshielded twisted pair (utp) cable, and h p auto mdi/mdi - x for reliable detection of and correction for straight - through and crossover cab les. on the mac processor side, the ksz80 9 1mnx offers the media independent interface (mii) and the ksz80 9 1rnb offers the reduced media independent interface (rmii) for direct connection with mii and rmii compliant ethernet mac processors and switches, res pectively. the mii management bus option gives the mac processor complete access to the ksz80 9 1 control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll for phy status change. the ksz80 9 1mnx/rnb is used to refer to both ksz80 9 1mnx and ksz80 91rnb versions in this data sheet. 100base - tx transmit the 100base - tx transmit function performs parallel - to - serial conversion, 4b/5b encoding, scrambling, nrz - to - nrzi conversion, and mlt3 encoding and transmission. the ci rcuitry starts with a parallel - to - serial conversion, which converts the mii /rmii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding and followed by a scrambler. the serialized data is further converted from nrz - to - nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 6.49k 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and complies with the ansi tp - pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave - shaped 10base - t output is also incorporated into the 100base - tx transmitter . 100base - tx receive the 100base - tx receiver function performs adaptive equalization, dc restoration , mlt3 - to - nrzi conversion, data and clock recovery, nrzi - to - nrz conversion, de - scrambling, 4b/5b decoding, and serial - to - parallel conversion. the receiving side starts with the equalization filter to compensate for inter - symbol interference (isi) over the twisted pair cable. because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on compa risons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an ongoing process and self - adjusts against environmental changes such as temperature variations. next, the equalized signal goes throu gh a dc - restoration and data - conversion block. the dc - restoration circuit compensates for the effect of baseline wander and improves the dynamic range. the differential data - conversion circuit converts mlt3 format back to nrzi. the slicing threshold is als o adaptive. the clock - recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then us ed to convert the nrzi signal to nrz format. this signal is sent through the de - scrambler, then the 4b/5b decoder. finally, t he nrz serial data is converted to mii /rmii format and provided as the input data to the mac. scrambler/de - scrambler (100base - tx only) the scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (emi) and basel ine wander. the de - scramble r recovers the scrambled signal . 10base - t transmit the 10base - t drivers are incorporated with the 100base - tx drivers to allow for transmission using the same magnetic. the drivers perform internal wave - shaping and pre - emphasis, a nd output 10base - t signals with a typical amplitude of 2.5v peak for standard 10base - t mode and 1.75v peak for energy - efficient 10base - te mode . the 10base - t /10base - te signals have harmonic contents that are at least 27db below the fundamental frequency whe n driven by an all - ones manchester - encoded signal.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 19 revision 1. 2 10base - t receive on the receive side, input buffer and level detecting squelch circuits are used. a differential input receiver circuit and a phase - locked loop (pll) performs the decoding function. the man chester - encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv, or with short pulse widths, to prevent noise at the rxp and rxm inputs from falsely triggering the decoder. when the inp ut exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8091mnx/rnb decodes a data frame. the receive clock is kept active during idle periods between data receptions. sqe and jabber function (10base - t only) in 10base - t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe test is needed to test the 10base - t transmit/receive path. if transmit enable (txen) is high for more than 20ms (jabbering), the 10base - t transmitter is disabled and col is as serted high. if txen is then driven low for more than 250ms, the 10base - t transmitter is re - enabled and col is de - asserted (returns to low). pll clock synthesizer the ksz80 9 1mnx/rnb generates all internal clocks and all external clocks for system timing fr om an external 25mhz crystal, oscillator, or reference clock. for the ksz80 9 1rnb in rmii 50mhz clock mode, these clocks are generated from an external 50mhz oscillator or system clock. auto - negotiation the ksz80 9 1mnx/rnb conforms to the auto - negotiation pr otocol, defined in clause 28 of the ieee 802.3 specification. auto - negotiation allows unshielded twisted pair (utp) link partners to select the highest common mode of operation. during auto - negotiation, link partners advertise capabilities across the utp link to each other and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest priority. ? priority 1: 100base - tx, full - duplex ? priority 2: 100base - tx, half - duplex ? priority 3: 10base - t, full - duplex ? priority 4: 10base - t, half - duplex if auto - negotiation is not supported or the ksz 80 9 1mnx/rnb link partner is forced to bypass auto - negotiation, then the ksz80 9 1mnx/rnb sets its operating mode by observing the signal at its receiver. this is known as parallel detection, which allows the ksz80 9 1mnx/rnb to establish a link by listening fo r a fixed signal protocol in the absence of the auto - negotiation advertisement protocol. auto - negotiation is enabled by either hardware pin strapping (nwayen, pin 30 ) or software (r egister 0h, bit [12]). by default, auto - negotiation is enabled after power - up or hardware reset. after that, auto - negotiation can be enabled or disabled by r egister 0h, bit [12]. if auto - negotiation is disabled, the speed is set by r egister 0h, bit [13], and the duplex is set by r egister 0h, bit [8]. the auto - negotiation link - up process is shown in figure 1 .
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 20 revision 1. 2 figure 1 . auto - negotiation flow chart
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 21 revision 1. 2 mii data interface (ksz809 1mnx o nly) the media independent interface (mii) is compliant with the ieee 802.3 specifi cation. it provides a common interface between mii phys and macs, and has the following key characteristics: ? pin count is 1 6 pins ( 7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication). ? 10mbps and 100mbps data rates are supported at both half - and full - duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 4 bits wide, a nibble. by default, the ksz80 9 1mnx is configured to mii mo de after it is powered up or hardware reset with the following: ? a 25mhz crystal connected to xi, xo (pins 9, 8), or an external 25mhz clock source (oscillator) connected to xi. ? the config[2:0] strapping pins (pins 18, 29, 28) set to 000 (default setting). mii signal definition table 1 describes the mii signals. refer to clause 22 of the ieee 802.3 specification for detailed information. table 1 . mii signal definition mii signal name directio n (with respect to phy, ksz80 9 1mnx signal) direction (with respect to mac) description txc output input transmit clock (2.5mhz for 10mbps; 25mhz for 100mbps) txen input output transmit enable txd[3:0] input output transmit data[3:0] txer input outpu t, or (not implemented) transmit error (ksz8091mnx implements only the eee function for this pin. see ? transmit error (txer)? for details.) rxc output input receive clock (2.5mhz for 10mbps; 25mhz for 100mbps) r xdv output input receive data valid rxd[3:0] output input receive data[3:0] rxer output input, or (not required) receive error crs output input carrier sense col output input collision detection transmit clock (txc) txc is sourced by the phy. it is a continuous clock that provides the timing reference for txen , txd[3:0] and txer. txc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. transmit enable (txen) txen indicates that the mac is presenting nibbles on txd[3:0] for transmission. it is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the mii. it is negated before the first txc following the final nibble of a frame. txen transitions synchronously wit h respect to txc.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 22 revision 1. 2 transmit data[3:0] (txd[3:0]) w hen txen is asserted, txd[3:0] are the data nibbles presented by the mac and accepted by the phy for transmission. when txen is de - asserted, the mac drives txd[3:0] to either 0000 for the idle state (non - ee e mode) or 0001 for the lpi state (eee mode). txd[3:0] transitions synchronously with respect to txc. transmit error (tx er ) txer is implemented only for the eee function. for eee mode, this pin is driven by the eee - mac to put the ksz8091mnx transmit into t he lpi state. for non - eee mode, this pin is not defined for error transmission from mac to ksz8091mnx and can be left as a no connect. txer transitions synchronously with respect to txc. receive clock (rxc) rxc provides the timing reference for rxdv, rxd[ 3:0] and rxer. ? in 10mbps mode, rxc is recovered from the line while the carrier is active. when the line is idle or the link is down, rxc is derived from the phy?s reference clock . ? in 100mbps mode, rxc is recovered continuously from the line. if the link i s down, rxc is derived from the phy?s reference clock. rxc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. receive data valid (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibbles on rxd[3:0]. ? in 10mbps mode, rxdv is asserted with the first nibble of the start - of - frame delimiter (sfd), 5d, and remains asserted until the end of the frame. ? in 100mbps mode, rxdv is asserted from the first nibble of the preamble to the last nibble of the frame. rxd v transitions synchronously with respect to rxc. receive data[3:0] (rxd[3:0]) for each clock period in which rxdv is asserted, rxd[3:0] transfers a nibble of recovered data from the phy. when rxdv is de - asserted, the phy drives rxd[3:0] to either 0000 for the idle state (non - eee mode) or 0001 for the lpi state (eee mode). rxd[3:0] transitions synchronously with respect to rxc. receive error (rxer) when rxdv is asserted, r xer is asserted for one or more rxc periods to indicate that a symbol error (for exam ple, a coding error that a phy can detect that may otherwise be undetectable by the mac sub - layer) i s detected somewhere in the frame that is being transferred from the phy to the mac . in eee mode only, when rxdv is de - asserted, rxer is driven by the phy to inform the mac that the ksz8091mnx receive is in the lpi state. rxer transitions synchronously with respect to rxc. carrier sense (crs) crs is asserted and de - asserted as follows: ? in 10mbps mode, crs assertion is based on the reception of valid preambl es. crs de - assertion is based on the reception of an end - of - frame (eof) marker.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 23 revision 1. 2 ? in 100mbps mode, crs is asserted when a start - of - stream delimiter or /j/k symbol pair is detected. crs is de - asserted when an end - of - stream delimiter or /t/r symbol pair is det ected. additionally, the pma layer de - asserts crs if idle symbols are received without /t/r. collision (col) col is asserted in half - duplex mode whenever the transmitter and receiver are simultaneously active on the line. this informs the mac that a collis ion has occurred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc. mii signal diagram the ksz80 9 1mnx mii pin connections to the mac are shown in figure 2 . figure 2 . ksz80 9 1mnx mii interface
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 24 revision 1. 2 rmii data interface (ksz80 9 1rnb o nly) the reduced media independent interface (rmii) specifies a low pin count media independent interface (mii). it provides a common interface between physical layer and m ac layer devices, and has the following key characteristics: ? pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50mhz reference clock). ? 10mbps and 100mbps data rates are supported at both half - and full - duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 2 bits wide, a dibit. rmii ? 25mhz clock mode the ksz80 9 1rnb is configured to rmii ? 25mhz clock mode after it is powered up or ha rdware reset with the following: ? a 25mhz crystal connected to xi, xo (pins 9, 8), or an external 25mhz clock source (oscillator) connected to xi. ? the config[2:0] strapping pins (pins 18, 29, 28) set to 001. ? register 1fh, bit [7] is set to 0 (default value) to select 25mhz clock mode. rmii ? 50mhz clock mode the ksz80 9 1rnb is configured to rmii ? 50mhz clock mode after it is powered up or hardware reset with the following: ? an external 50mhz clock source (oscillator) connected to xi (pin 9). ? the config[2:0] s trapping pins (pins 18, 29, 28) set to 001. ? register 1fh, bit [7] is set to 1 to select 50mhz clock mode. rmii signal definition table 2 describes the rmii signals. refer to rmii specification v1.2 for detailed inf ormation. table 2 . rmii signal definition rmii signal name direction (with respect to phy, ksz80 9 1rnb signal) direction (with respect to mac) description ref_clk output (25mhz clock mode) / (50mhz clock mode) input/ input or synchronous 50mhz reference clock for receive, transmit, and control interface txen input output transmit enable txd[1:0] input output transmit data[1:0] crs_dv output input carrier sense/receive data valid rxd[1:0] output input r eceive data[1:0] rxer output input, or (not required) receive error reference clock (ref_clk) ref_clk is a continuous 50mhz clock that provides the timing reference for txen, txd[1:0], crs_dv, rxd[1:0] and rx_er. for 25mhz clock mode, the ksz80 9 1rnb gen erates and outputs the 50mhz rmii ref_clk to the mac at ref_clk (pin 19). for 50mhz clock mode, the ksz80 9 1rnb takes in the 50mhz rmii ref_clk from the mac or system board at xi (pin 9) and leaves the ref_clk (pin 19) as a no connect.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 25 revision 1. 2 transmit enable (txen ) txen indicates that the mac is presenting dibits on txd[ 1 :0] for transmission. it is asserted synchronously with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the rmii. it is negated before the f irst ref_clk following the final dibit of a frame. txen transitions synchronously with respect to ref_clk. transmit data[1:0] (txd[1:0]) w hen txen is asserted , txd[1 :0] are the data dibits presented by the mac and accepted by the phy for transmission. whe n txen is de - asserted, the mac drives txd[1:0] to either 00 for the idle state (non - eee mode) or 01 for the lpi state (eee mode). txd[1:0] transitions synchronously with respect to ref_clk. carrier sense / receive data valid (crs_dv) the phy asserts crs_dv when the receive medium is non - idle. it is asserted asynchronously when a carrier is detected . this happens when squelch is passed in 10mbps mode, and when two non - contiguous 0s in 10 bits are detected in 100mbps mode. loss of carrier results in the de - as sertion of crs_dv. while carrier detection criteria are met, crs_dv remains asserted continuously from the first recovered dibit of the frame through the final recovered dibit. it is negated before the first ref_clk that follows the final dibit. the data o n rxd[1:0] is considered valid after crs_dv is asserted. however, because the assertion of crs_dv is asynchronous relative to ref_clk, the data on rxd[1:0] is 00 until receive si gnals are proper ly decod ed . receive data[1:0] (rxd[1:0]) f or each clock period in which crs_dv is asserted, rxd[1 :0] transfers a dibit of recovered data from the phy. when crs_dv is de - asserted, the phy drives rxd[1:0] to either 00 for the idle state (non - eee mode) or 01 for the lpi state (eee mode). rxd[1 :0] transitions synchrono usly with respect to ref_clk. receive error (rxer) when crs_dv is asserted, rxer is asserted for one or more ref_clk periods to indicate that a symbol error (for example, a coding error that a phy can detect that may otherwise be undetectable by the mac su b - layer) i s detected somewhere in the frame that is being transferred from the phy to the mac . rxer transitions synchronously with respect to ref_clk. collision detection (col) the mac regenerates the col signal of the mii from txen and crs_dv. rmii signal diagram the ksz80 9 1rnb rmii pin connections to the mac for 25mhz clock mode are shown in figure 3 . the connections for 50mhz clock mode are shown in figure 4 .
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 26 revision 1. 2 figure 3 . ksz80 9 1rnb rmii interface (25mhz clock mode) figure 4 . ksz80 9 1rnb rmii interface (50mhz clock mode)
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 27 revision 1. 2 back -to- back mode ? 100mbps copper repeater two ksz80 9 1mnx/rnb devices can be connected back - to - bac k to for m a 100base - tx copper repeater. figure 5 . ksz80 9 1mnx/rnb to ksz80 9 1mnx/rnb back - to - back copper repeater mii back - to - back mode (ksz80 9 1mnx o nly) in mii back - to - back mode, a ksz80 9 1mnx interfaces with another ksz80 9 1mnx to provide a complete 100mbps copper repeater solution. t he ksz80 9 1mnx devices are configured to mii back - to - back mode after power - up or reset with the following: ? strapping pin config[2:0] (pins 18, 29, 28) set to 110 ? a common 25mhz reference clock connect ed to xi (pin 9) of both ksz80 9 1mnx devices ? mii signals connected as shown in table 3 table 3 . mii signal connection for mii back -to - back mode (100base- tx copper repeater) ksz80 9 1mnx (100ba se- tx copper) [device 1] ksz80 9 1mnx (100base - tx copper) [device 2] pin name pin number pin type pin name pin number pin type rxc 19 output txc 22 input rxdv 18 output txen 23 input rxd3 13 output txd3 27 input rxd2 14 output txd2 26 input rxd1 15 out put txd1 25 input rxd0 16 output txd0 24 input txc 22 input rxc 19 output txen 23 input rxdv 18 output txd3 27 input rxd3 13 output txd2 26 input rxd2 14 output txd1 25 input rxd1 15 output txd0 24 input rxd0 16 output
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 28 revision 1. 2 rmii back - to - back mode (ksz8 0 9 1rnb o nly) in rmii back - to - back mode, a ksz80 9 1rnb interfaces with another ksz80 9 1rnb to provide a complete 100mbps copper repeater solution. t he ksz80 9 1rnb devices are configured to rmii back - to - back mode after power - up or reset with the following: ? stra pping pin config[2:0] (pins 18, 29, 28) set to 101 ? a common 50mhz reference clock connected to xi (pin 9) of both ksz80 9 1rnb devices ? rmii signals connected as shown in table 4 table 4 . rmii signal connection for rmii back -to - back mode (100base- tx copper repeater) ksz80 9 1rnb (100base - tx copper) [device 1] ksz80 9 1rnb (100base - tx copper) [device 2] pin name pin number pin type pin name pin number pin type crsdv 18 output txen 23 input rxd1 1 5 output txd1 25 input rxd0 16 output txd0 24 input txen 23 input crsdv 18 output txd1 25 input rxd1 15 output txd0 24 input rxd0 16 output
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 29 revision 1. 2 mii management (miim) interface the ksz80 9 1mnx/rnb supports the ieee 802.3 mii management interface, also know n as the management data input/output (mdio) interface. this interface allows an upper - layer device, such as a mac processor, to monitor and control the state of the ksz80 9 1mnx/rnb. an external device with miim capability is used to read the phy status and /or configure the phy settings. more details about the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates the clock line (mdc) and the data lin e (mdio). ? a specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communicate with one or more phy devices. ? a 32 - register address space for direct access to ieee - defined registers and vend or - specific registers, and for indirect access to mmd addresses and registers. see the ? register map ? section. as the default, the ksz80 9 1mnx/rnb supports unique phy addresses 1 to 7, and broadcast phy address 0. t he latter is defined in the ieee 802.3 specification, and can be used to read/write to a single ksz80 9 1mnx/rnb device, or write to multiple ksz80 9 1mnx/rnb devices simultaneously. phy address 0 can optionally be disabled as the broadcast address by either h ardware pin strapping (b - cast_off, pin 19) or software (r egister 16h, bit [9]), and assigned as a unique phy address. the phyad[2:0] strapping pins are used to assign a unique phy address between 0 and 7 to each ksz80 9 1mnx/rnb device. the miim interface ca n operates up to a maximum clock speed of 10mhz mac clock. table 5 shows the mii management frame format for the ksz80 9 1mnx/rnb. table 5 . mii management frame format for the ksz80 9 1mnx/rnb preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z interrupt (intrp) intrp (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the ksz80 9 1mnx/rnb phy register. bits [15:8] of r egister 1bh are the interrupt control bits to enable and disable the conditions for a sserting the intrp signal. bits [7:0] of r egister 1bh are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading r egister 1bh. bit [9] of r egister 1fh sets the interrupt level to active high or active low. the default is active low. the mii management bus option gives the mac processor complete access to the ksz80 9 1mnx/rnb control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll the phy for status change.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 30 revision 1. 2 hp auto mdi/mdi -x hp auto mdi/mdi - x configuration eliminates the need to decide whether to use a straight cable or a crossover cable between the ksz80 9 1mnx/rnb and its link partner. this feature allows the ksz80 9 1mnx/rnb to use eith er type of cable to connect with a link partner that is in either mdi or mdi - x mode. the auto - sense function detects transmit and receive pairs from the link partner and assigns transmit and receive pairs to the ksz80 9 1mnx/rnb accordingly. hp auto mdi/mdi - x is enabled by default. it is disabled by writing a ?1? to r egister 1fh, bit [13]. mdi and mdi - x mode is selected by r egister 1fh, bit [14] if hp auto mdi/mdi - x is disabled. an isolation transformer with symmetrical transmit and receive data paths is reco mmended to support auto mdi/mdi - x. table 6 shows how the ieee 802.3 standard defines mdi and mdi - x. table 6 . mdi/mdi - x pin definition mdi mdi -x rj - 45 pin signal rj - 45 pin signal 1 tx+ 1 r x+ 2 tx ? 2 rx ? 3 rx+ 3 tx+ 6 rx ? 6 tx ? straight cable a straight cable connects an mdi device to an mdi - x device, or an mdi - x device to an mdi device. figure 6 shows a typical straight cable connection between a nic card (mdi device) and a switch or hub (mdi - x device). figure 6 . typical straight cable connection
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 31 revision 1. 2 crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi - x device to another mdi - x devic e. figure 7 shows a typical crossover cable connection between two switches or hubs (two mdi - x devices). figure 7 . typical crossover cable connection
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 32 revision 1. 2 loopback mode th e ksz80 9 1mnx/rnb supports the following loopback operations to verify analog and/or digital data paths. ? local (digital) loopback ? remote (analog) loopback local (digital) loopback this loopback mode checks the mii/rmii transmit and receive data paths betwee n the ksz80 9 1mnx/rnb and the external mac, and is s upported for both speeds (10/100mbps) at full - duplex. the loopback data path is shown in figure 8 . 1. the mii/rmii mac transmits frames to the ksz80 9 1mnx/rnb. 2. frames are wrapped around inside the ksz80 9 1mnx/rnb. 3. the ksz80 9 1mnx/rnb transmits frames back to the mii/rmii mac. 4. except the frames back to the rmii mac , the transmit frames also go out from the copper port. figure 8 . local (digital) loopback the following programming action and register settings are used for local loopback mode. for 10/100 mbps loopback, set r egister 0h, ? bit [14] = 1 // enable local loopback mode ? bit [13] = 0/1 // select 10mbps/100mbps speed ? bit [12] = 0 // di sable auto - negotiation ? bit [8] = 1 // select full - duplex mode
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 33 revision 1. 2 remote (analog) loopback this loopback mode checks the line (differential pairs, transformer, rj - 45 connector, ethernet cable) transmit and receive data paths between the ksz80 9 1mnx/rnb and its link partner, and is s upported for 100base - tx full - duplex mode only. the loopback data path is shown in figure 9 . 1. the fast ethernet (100base - tx) phy link partner transmits frames to the ksz80 9 1mnx/rnb. 2. fram es are wrapped around inside the ksz80 9 1mnx/rnb. 3. the ksz80 9 1mnx/rnb transmits frames back to the fast ethernet (100base - tx) phy link partner. figure 9 . remote (analog) loopback the following programming steps and register sett ings are used for remote loopback mode. 1. set register 0h, ? bits [13] = 1 // select 100mbps speed ? bit [12] = 0 // disable auto - negotiation ? bit [8] = 1 // selec t full - duplex mode or just auto - negotiate and link up with the link partner at 100base - tx fu ll- duplex mode . 2. set register 1fh, ? bit [2] = 1 // enable remote loopback mode
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 34 revision 1. 2 linkmd ? cable diagnostic the linkmd function uses time - domain reflectometry (tdr) to analyze the cabling plant for common cabling problems. these include open circuits , short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi or mdi - x pair, then analyzing the shape of the reflected signal to determine the type of fault . the time duration for the reflected sig nal to return provides the approximate distance to the cabling fault . the linkmd function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd is initiated by accessing register 1dh, the lin kmd c able diagnostic register, in conjunction with register 1fh, the phy control 2 r egister. the latter register is used to disable auto mdi/mdi - x and to select either mdi or mdi - x as the cable differential pair for testing. usage the following is a sample procedure for using linkmd with registers 1dh and 1fh: 3. disable auto mdi/mdi - x by wr iting a ?1? to register 1fh, bit [13 ] . 4. start cable diagnostic test by wr iting a ?1? to register 1dh, bit [ 15 ]. this enable bit is self - clearing. 5. wait (poll) for register 1 dh , bit [ 15 ] to return a ?0?, and indicating cable diagnostic test is completed. 6. read cable diagnostic test results in register 1dh , bits [ 14: 13 ]. the results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) the ?11? case, invalid test, occurs when the device is unable to shut down the link partner. in this instance, the test is not run, since it would b e impossible for the device to determine if the detected signal is a reflection of the signal generated or a signal from another source. 7. get distance to fault by concatenating register 1dh, bits [ 8:0 ] and multiplying the result by a constant of 0. 38 . the distance to the cable fault can be determined by the following formula: d (distance to cable fault) = 0.38 x (register 1 d h, bits [8:0]) d (distance to cable fault) is expressed in meters. concatenated value of registers 1dh bit s [ 8 :0] should be converted to decimal before multiplying by 0. 38. the constant (0. 38 ) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 35 revision 1. 2 nand tree support the ksz80 9 1mnx/rnb provides pa rametric nand tree support for fault detection between chip i/os and board. the nand tree is a chain of nested nand gates in which each ksz80 9 1mnx/rnb digital i/o (nand tree input) pin is an input to one nand gate along the chain. at the end of the chain, the crs/config1 pin provides the output for the nested nand gates. the nand tree test process includes: ? enabling nand tree mode ? pulling all nand tree input pins high ? driving each nand tree input pin low, sequentially, according to the nand tree pin order ? c hecking the nand tree output to make sure there is a toggle high - to - low or low - to - high for each nand tree input driven low table 7 and table 8 list the nand tree pin order s for ksz80 9 1mnx and ksz80 9 1rnb, respectively. table 7 . nand tree test pin order for ksz80 9 1mnx pin number pin name nand tree description 11 mdio input 12 mdc input 13 rxd3 input 14 rxd2 input 15 rxd1 input 16 rxd0 input 18 rxdv input 19 rxc input 20 rxer input 21 intrp input 22 txc input 23 txen input 24 txd0 input 25 txd1 input 26 txd2 input 27 txd3 input 30 led0 input 28 col input 29 crs output
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 36 revision 1. 2 table 8 . nand tree test pin order for k sz80 9 1rnb pin number pin name nand tree description 11 mdio input 12 mdc input 13 phyad0 input 14 phyad1 input 15 rxd1 input 16 rxd0 input 18 crs_dv input 19 ref_clk input 20 rxer input 21 intrp input 22 pme_en input 23 txen input 24 txd0 inpu t 25 txd1 input 30 led0 input 31 led1 input 28 config0 input 29 config1 output nand tree i/o testing use the following procedure to check for faults on the ksz80 9 1mnx/rnb digital i/o pin connections to the board: 1. enable nand tree mode using either h ardware (na nd_tree#, pin 21) or software (r egister 16h, bit [5]). 2. use board logic to drive all ksz80 9 1mnx/rnb nand tree input pins high. 3. use board logic to drive each nand tree input pin, in ksz80 9 1mnx/rnb nand tree pin order, as follows: a. toggle the first pin (mdio) from high to low, and verify that the crs/config1 pin switches from high to low to indicate that the first pin is connected properly. b. leave the first pin (mdio) low. c. toggle the second pin (mdc) from high to low, and verify that the crs/config1 p in switches from low to high to indicate that the second pin is connected properly. d. leave the first pin (mdio) and the second pin (mdc) low. e. toggle the third pin (rxd3 /phyad0)) from high to low, and verify that the crs/config1 pin switches from high to low to indicate that the third pin is connected properly. f. continue with this sequence until all ksz80 9 1mnx/rnb nand tree input pins have been toggled. each ksz80 9 1mnx/rnb nand tree input pin must cause the crs/config1 output pin to toggle high - to - low or low - t o - high to indicate a good connection. if the crs /config1 pin fails to toggle when the ksz80 9 1mnx/rnb input pin toggles from high to low, the input pin has a fault.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 37 revision 1. 2 power management the ksz80 9 1mnx/rnb incorporates a number of power - management modes and fe atures that provide methods to consume less energy. these are discussed in the following sections. power - saving mode power - saving mode is used to reduce the transceiver power consumption when the cable is unplugged. it is enabled by writing a ?1? to r egist er 1fh, bit [10], and is in effect when auto - negotiation mode is enabled and the cable is disconnected (no link). in this mode, the ksz80 9 1mnx/rnb shuts down all transceiver blocks, except for the transmitter, energy detect, and pll circuits. by default, power - saving mode is disabled after power - up. energy - detect power - down mode energy - detect power - down (edpd) mode is used to further reduce transceiver power consumption when the cable is unplugged. it is enabled by writing a ?0? to r egister 18h, bit [11], and is in effect when auto - negotiation mode is enabled and the cable is disconnected (no link). edpd mode works with the pll off (set by writi ng a ?1? to r egister 10h, bit [4] to automatically turn the pll off in edpd mode) to turn off all ksz80 9 1mnx/rnb transceiver blocks except the transmitter and energy - detect circuits. power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. the periodic transmission of link pulses is needed to ensure the ksz80 9 1mnx/rnb and its link partner, when operating in the same low - power state and with auto mdi/mdi - x disabled, can wake up when the cable is connected between them. by default, energy - detect power - down mode is disabled after power - up. power - down mode power - down mode is used to power down the ksz80 9 1mnx/rnb device when it is not in use after power - up. it is enabled by writi ng a ?1? to r egister 0h, bit [11]. in this mode, the ksz80 9 1mnx/rnb disables all internal functions except the mii management interface. the ksz80 9 1mnx/rnb exits (d isables) power - down mode after r egister 0h, bit [11] is set back to ?0?. slow - oscillator mode slow - oscillator mode is used to disconnect the input reference crystal/clock on xi (pin 9 ) and select the on - chip slow oscillator when the ksz80 9 1mnx/rnb device is not in use after power - up. it is enabled by writing a ?1? to r egister 11h, bit [5]. slow - oscillator mode works in conjunction with power - down mode to put the ksz80 9 1mnx/rnb device in the lowest power s tate , with all internal functions disabled except the mii management interface. to properly exit this mode and return to normal phy operation, use the following programming sequence: 1. disable slow - oscillator mode by writing a ?0? to r egister 11h, bit [5]. 2. d isable power - down mode by writing a ?0? to r egister 0h, bit [11]. 3. initiate soft ware reset by writing a ?1? to r egister 0h, bit [15].
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 38 revision 1. 2 energy efficient ethernet (eee) the ksz 8091mnx implements energy efficient ethernet (e ee) for the media independent interf ace (mii) as described in ieee standard 802.3az . the s tandard is defined around a n eee - compliant mac on the host side and an eee - compliant link p artner on the line side that support special signaling associated with eee. eee saves power by keeping the ac s ignal on the copper ethernet cable at approximately 0v peak - to - peak as often as possible during periods of no traffic activ ity, while maintaining the link - up status. this is referred to as low - p ower i dle (lpi) mode or state . similarly, the ksz8091rnb impl ements eee for the reduced media independent interface (rmii) a s described in ieee standard 802.3az for line signaling by the two differential pairs (analog side) and according to the multisource agreement (msa) of collaborating fast ethernet chip vendors for the r mii (digital side). this agreement is based on the ieee standard?s eee implementation for mii (100mbps). during lpi mode, the copper link respond s automatically when it receives traffic and resume s normal phy operation immediately, without blocka ge of traffic or loss of packet . this involves e xiting lpi mode and returning to normal 100mbps operating mode. wake - up time is <30 s for 100b ase - t x. the lpi state is controlled independently for transmit and receive paths, allowing the lpi state to be act ive (enabled) for: ? transmit cable path only ? receive cable path only ? both transmit and receive cable paths the ksz 8091mnx/rnb has the eee function disabled as the power - up default setting. to enable the eee function for 100mbps mode, use the following prog ramming sequence: 1. enable 100mbps eee mode advertisement by wr iting a ?1? to mmd address 7h, r egister 3ch, bit [1]. 2. restart auto - negotiation by wr iting a ?1? to standard r egister 0h, b it [9]. for standard (non - eee) 10base - t mode, normal link pulses (nlps) w ith long periods of no ac signal transmission are used to maintain the link during the idle period when there is no traffic activity. to save more power, the ksz 8091mnx/rnb provides the option to enable 10base - te mode, which saves additional power by reduc ing the transmitted signal amplitude from 2.5v to 1.75v. to enable 10base - te mode, write a ?1? to standard r egister 13 h, bit [ 4 ]. during lpi mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. approximately eve ry 20 to 22 milliseconds, a refresh transmission of 200 to 220 microseconds is sent to the link partner. the refresh transmissions and quiet periods are shown in figure 10 . figure 10 . l pi mode (refresh transmissions and quiet periods)
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 39 revision 1. 2 transmit direction control (mac - to - phy) the ksz 8091mnx enters lpi mode for the transmit direction when its attached eee - compliant mii mac de - asserts tx en, asser ts txer, and sets txd[3:0] to 0001. the ksz80 91 mnx remains in the lpi transmit state while the mac maintains the states of these signals. whe n the mac changes any of the txen, tx er, or tx data signals from the ir lpi state values, the ksz8091 mnx exit s the lpi transmit state. the txc clock is not stopp ed, because it is sourced from the phy and is used by the mac for mii transmit. figure 11 shows the lpi transition for mii (100mbps) transmit. figure 11 . lpi transition ? mii (100mbps) transmit similarly, the ksz8091rnb enters lpi mode for the transmit direction when its attached eee - compliant rmii mac de - asserts txen and sets txd [1:0] to 01. the ksz8091rnb remain s in the lpi transmit state while the rmii mac maintains the states of th ese signals. whe n the rmii mac changes any of the txen or tx data signals from the ir lpi state values, the ksz8091rnb exit s the lpi transmit state. figure 12 shows the lpi transition for rmii (100mbps) transmi t. figure 12 . lpi transition ? rmii (100mbps) transmit
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 40 revision 1. 2 receive direction control (phy - to - mac) the ksz 8091mnx enters lpi mode for the receive direction when it receives the /p/ code bit pattern (sleep/refresh) from its eee - compliant link partner . it then de - assert s rx dv, assert s rx er , and drive s rxd[3:0] to 0001 . the ksz 8091m nx rem ain s in the lpi receive state while it continues to rece ive the r efresh from its link partner, so it will continue to maintain and drive the lpi output sta tes for th e mii receive signals to inform the attached eee - compliant mii mac that it is in the lpi rec eive state. when the ksz8091 mnx receives a non /p / code bit pattern (non - r efresh), it exits the lpi receive state and sets the rxdv, rx er , and rx data sig nals to set a normal frame or normal idle. the ksz8091mnx stops the rxc clock output to the mac after nine or more rxc clock cycles have occurred in the lpi receive state , to save more power. by default, rxc clock stoppage is enabled. i t is disabled by wri ting a ?0 ? to mmd address 3h, r egister 0h, b it [10 ] . figure 13 shows the lpi transition for mii (100mbps) receive . figure 13 . lpi transition ? mii (100mbps) receive similarly, the ksz8 091rnb enters lpi mode for the receive direction when it receives the /p/ code bit pattern (sleep/refresh) from its eee - compliant link partner. it then de - assert s crs_dv and drives rxd[1:0] to 01. the ksz 8091rnb remains in the lpi receive state while it co ntinues to receive the refresh from its link partner, so it will continue to maintain and drive the lpi output states for the r mii receive signals to inform the attached eee - compliant r mii mac that it is in the lpi receive state. when the ksz8091 rnb receiv es a non /p/ code bit pattern (non - refresh), it exits the lpi receive state and sets the crs_dv and rx data signals to set a normal frame or normal idle. figure 14 shows the lpi transition for rmii (100mbps) receiv e . figure 14 . lpi transition ? rmii (100mbps) receive
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 41 revision 1. 2 registers associated with eee the following registers are provided for eee configuration and management: ? standard r egister 13h - afe control 4 (to enable 10base - te mode) ? mmd address 1 h, r egister 0h - pma/pmd control 1 (to enable lpi) ? mmd address 1h, r egister 1h - pma/pmd status 1 (for lpi status) ? mmd address 3 h, r egister 0h - eee pcs control 1 (to stop rxc clock for ksz8091mnx only) ? mmd address 7h, r egister 3ch - eee advertisement ? mmd address 7h, r egister 3dh - eee link partner advertisement
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 42 revision 1. 2 wake -o n- lan wake - o n - lan (wol) is normally a mac - based function to wake up a host system (for example, an ethernet end device, such as a pc) that is in standby power mode. w ake - up is triggered by receiving and detecting a special packet (commonly referred to as the ?magic packet?) that is sent by the remote link partner. the ksz 8091mnx/rnb can perform the same wol function if the mac address of its associated mac device is en tered into the ksz 8091mnx/rnb phy registers for magic - packet detection. when the ksz 8091mnx/rnb detects the magic packet, it wakes up the host by driving its power management event (pme) output pin low. by default, the wol function is disabled. it is enabl ed by setting the enabling bit and configuring the associated registers for the selected pme wake - up detection method. the ksz 8091mnx/rnb provides three methods to trigger a pme wake - up: ? magic - packet detection ? customized - packet detection ? link status change detection magic - packet detection the magic packet?s frame format starts with 6 bytes of 0xffh and is followed by 16 repetitions of the mac address of its associated mac device (local mac device). when the magic packet is detected from its link partner, th e ksz 8091mnx/rnb asserts its pme output pin low. the following mmd address 1fh registers are provided for magic - packet detection: ? magic - packet detection is enabled by wri ting a ?1? to mmd address 1fh, r egister 0h, bit [6] ? the mac address (for the local mac device) is written to and stored in mmd address 1fh, r egisters 19h ? 1bh the ksz 8091mnx/rnb does not generate the magic packet. the magic packet must be provided by the external system.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 43 revision 1. 2 customized - packet detection the customized packet has associated regi ster/bit masks to select which byte, or bytes, of the first 64 bytes of the packet to use in the crc calculation. after the ksz 8091mnx/rnb receives the packet from its link partner, the selected bytes for the received packet are used to calculate the crc. the calculated crc is compared to the expected crc value that was previously written to and stored in the ksz 8091mnx/rnb phy r egisters. if there is a match, the ksz 8091mnx/rnb asserts its pme output pin low. four customized packets are provided to support four types of wake - up scenarios. a dedicated set of registers is used to configure and enable each customized packet. the following mmd r egisters are provided for customized - packet detection: ? each of the four customized packets i s enabled via mmd address 1 fh, r egister 0h, ? bit [2] // for customized packets, type 0 ? bit [3] // for customized packets, type 1 ? bit [4] // for customized packets, type 2 ? bit [5] // for customized packets, type 3 ? masks to indicate which of the first 64 - bytes to use in the crc calcu lation are set in: ? mmd address 1fh, r egisters 1h ? 4h // for customized packets, type 0 ? mmd address 1fh, re gisters 7h ? ah // for customized packets, type 1 ? mmd address 1fh, r egisters dh ? 10h // for customized packets, type 2 ? mmd address 1fh, r egisters 13 h ? 16h // for customized packets, type 3 ? 32- bit expected crcs are written to and stored in: ? mmd address 1fh, r egisters 5h ? 6h // for customized packets, type 0 ? mmd address 1fh, r egisters bh ? ch // for customized packets, type 1 ? mmd address 1fh, r egister s 11h ? 12h // for customized packets, type 2 ? mmd address 1fh, r egisters 17h ? 18h // for customized packets, type 3 link status change detection if link status change detection is enabled, the ksz 8091mnx/rnb asserts its pme output pin low whenever there i s a link status change, using the following mmd address 1fh register bits and their enabled (1) or disabled (0) settings: ? mmd address 1fh, r egister 0h, bit [0] // for link - up detection ? mmd address 1fh, r egister 0h, bit [1] // for link - down detection the p me output signal is available on either intrp/pme_n2 (pin 21) or led0/pme_n1 (pin 30), and is enabled using s tandard r egister 16h, bit [15]. mmd add ress 1fh, r egister 0h, bits [15:14] defines and selects the output functions for pins 21 and 30. the pme out put is active low and requires a 1k pull - up to the vddio supply. when asserted, the pme output is cleared by disabling the register bit that enabled the pme trigger source (magic packet, customized packet, link status change).
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 44 revision 1. 2 reference circuit for po wer and ground connections the ksz80 9 1mnx/rnb is a single 3.3v supply device with a built - in regulator to supply the 1.2v core. the power and ground connections are shown in figure 15 and table 9 for 3.3v vddio. figure 15 . ksz80 9 1mnx/rnb power and ground connections table 9 . ksz80 9 1mnx/rnb power pin description power pin pin number description vdd_1.2 2 decouple with 2. 2 f and 0.1 f capacitors to ground. vdda_3.3 3 connect to board?s 3.3v supply through a ferrite bead. decouple with 22 f and 0.1 f capacitors to ground. vddio 17 connect to board?s 3.3v supply for 3.3v vddio. decouple with 22 f and 0.1 f capacitors to gr ound.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 45 revision 1. 2 typical current/power consumption table 10 through table 12 show typical values for current consumption by the transceiver (vdda_3.3) and digital i/o (vddio) powe r pins , and typical values for power consumption by the ksz80 9 1mnx/rnb device for the indicated nominal operating voltages. these current and power consumption values include the transmit driver current and on - chip regulator current for the 1.2v core. tran sceiver (3.3v), digital i/os (3.3v) table 10 . typical current/power consumption (vdda_3.3 = 3.3v, vddio = 3.3v) condition 3.3v transceiver (vdda_3.3) 3.3v digital i/os (vddio) total chip power ma ma mw 100base - tx link - up (no tra ffic) 34 12 152 100base - tx full - duplex @ 100% utilization 34 13 155 10base - t link - up (no traffic) 14 11 82.5 10base - t full - duplex @ 100% utilization 30 11 135 eee 100mbps link - up mode (transmit and receive in lpi state with no traffic) 13 10 75.9 powe r- saving mode (reg. 1fh, bit [10] = 1) 1 3 10 7 5.9 edpd mode (reg. 18h, bit [11] = 0) 10 10 66.0 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.77 1.54 17.5 software power - down mode (reg. 0h, bit [11] =1) 2.59 1.51 13.5 softwar e power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.36 0.45 5.97 transceiver (3.3v), digital i/os (2.5v) table 11 . typical current/power consumption (vdda_3.3 = 3.3v, vddio = 2.5v) condition 3.3v transceiver (vdda_3.3) 2.5v digital i/os (vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 11 140 100base - tx full - duplex @ 100% utilization 34 12 142 10base - t link - up (no traffic) 15 10 74.5 10base - t full - duplex @ 100% utiliz ation 27 10 114 eee 100mbps link - up mode (transmit and receive in lpi state with no traffic) 13 10 67.9 power - saving mode (reg. 1fh, bit [10] = 1) 1 3 10 67.9 edpd mode (reg. 18h, bit [11] = 0) 11 10 61.3 edpd mode (reg. 18h, bit [11] = 0) and pll off ( reg. 10h, bit [4] = 1) 3.55 1.35 15.1 software power - down mode (reg. 0h, bit [11] =1) 2.29 1.34 10.9 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.15 0.29 4.52
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 46 revision 1. 2 transceiver (3.3v), digital i/os (1.8v) table 12 . typical current/power consumption (vdda_3.3 = 3.3v, vddio = 1.8v) condition 3.3v transceiver (vdda_3.3) 1.8v digital i/os (vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 11 132 100base - tx full -du plex @ 100% utilization 34 12 134 10base - t link - up (no traffic) 15 9.0 65.7 10base - t full - duplex @ 100% utilization 27 9.0 105 eee 100mbps link - up mode (transmit and receive in lpi state with no traffic) 13 9.0 59.1 power - saving mode (reg. 1fh, bit [10 ] = 1) 13 9.0 59.1 edpd mode (reg. 18h, bit [11] = 0) 11 9.0 52.5 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 4.05 1.21 15.5 software power - down mode (reg. 0h, bit [11] =1) 2.79 1.21 11.4 software power - down mode (reg. 0h, bi t [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.65 0.19 5.79
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 47 revision 1. 2 register map the register space within t he ksz8091mnx/rnb consists of two distinct areas. ? standard registers // direct register access ? mdio ma nageable device (mmd) registers // indirect register access the ksz8091mnx/rnb supports the following standard registers. table 13 . standard registers supported by ksz8091mnx/rnb register number (hex) description ieee - defined registers 0h basic control 1h bas ic status 2h phy identifier 1 3h phy identifier 2 4h auto - negotiation advertisement 5h auto - negotiation link partner ability 6h auto - negotiation expansion 7h auto - negotiation next page 8h auto - negotiation link partner next page ability 9 h ? ch rese rved dh mmd access ? control eh mmd access ? register/data fh reserved vendor - specific registers 10h digital reserved control 11h afe control 1 12h reserved 13h afe control 4 14h reserved 15h rxer counter 16h operation mode strap override 17h o peration mode strap status 18h expanded control 1 9 h ? 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd cable diagnostic 1eh phy control 1 1fh phy control 2
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 48 revision 1. 2 the ksz 8091mnx/rnb supports the following mmd device addresses and their associated register addresses, which make up the indirect mmd registers. table 14 . mmd registers supported by ksz8091mnx/rnb device address (hex) register address (hex) description 1h 0h pma/pmd control 1 1h pma/pmd status 1 3h 0h eee pcs control 1 7h 3ch eee advertisement 3dh eee link partner advertisement 1f h 0h wake - on - lan ? control 1h wake - on - lan ? customized packet, type 0, mask 0 2h wake - on - lan ? customized packet, type 0, mask 1 3h wake - on - lan ? customized pac ket, type 0, mask 2 4h wake - on - lan ? customized packet, type 0, mask 3 5h wake - on - lan ? customized packet, type 0, expected crc 0 6h wake - on - lan ? customized packet, type 0, expected crc 1 7h wake - on - lan ? customized packet, type 1, mask 0 8h wak e - on - lan ? customized packet, type 1, mask 1 9h wake - on - lan ? customized packet, type 1, mask 2 ah wake - on - lan ? customized packet, type 1, mask 3 bh wake - on - lan ? customized packet, type 1, expected crc 0 ch wake - on - lan ? customized packet, type 1 , expected crc 1 dh wake - on - lan ? customized packet, type 2, mask 0 eh wake - on - lan ? customized packet, type 2, mask 1 fh wake - on - lan ? customized packet, type 2, mask 2 10h wake - on - lan ? customized packet, type 2, mask 3 11h wake - on - lan ? custom ized packet, type 2, expected crc 0 12h wake - on - lan ? customized packet, type 2, expected crc 1 13h wake - on - lan ? customized packet, type 3, mask 0 14h wake - on - lan ? customized packet, type 3, mask 1 15h wake - on - lan ? customized packet, type 3, mas k 2 16h wake - on - lan ? customized packet, type 3, mask 3 17h wake - on - lan ? customized packet, type 3, expected crc 0 18h wake - on - lan ? customized packet, type 3, expected crc 1 19h wake - on - lan ? magic packet, mac -da -0 1ah wake - on - lan ? magic packe t, mac -da -1 1bh wake - on - lan ? magic packet, mac -da -2
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 49 revision 1. 2 standard r egister s standard registers provide direct read/write access to a 32 - register address space, as defined in clause 22 of the ieee 802.3 specification. within this address space, the first 1 6 registers (r egisters 0h to fh) are defined according to the ieee specification, while the remaining 16 registers ( r egisters 10h to 1fh) are defined specific to the phy vendor. ieee - defined registers ? descriptions address name description mode ( 9 ) default register 0h ? basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self - cleared after a ?1? is written to it. rw/sc 0 0.14 loopback 1 = loopback mode 0 = normal operation rw 0 0.13 s peed select 1 = 100mbps 0 = 10mbps this bit is ignored if auto - negotiation is enabled (register 0.12 = 1). rw set by the speed strapping pin (ksz8091rnb only) . see the ? strapping options ? ksz8091rnb ? section for d etails. 0.12 auto - negotiation enable 1 = enable auto - negotiation process 0 = disable auto - negotiation process if enabled, the auto - negotiation result overrides the settings in r egisters 0.13 and 0.8. rw set by the nwayen strapping pin. see the ? strapping options ? ksz8091mnx ? section for details. 0.11 power - down 1 = power - down mode 0 = normal operation if software reset ( r egister 0.15) is used to exit power - down mode ( r egister 0.11 = 1), two software reset writes (r egister 0.15 = 1) are required. the first write clears power - down mode; the second write resets the chip and re - latches the pin strapping pin values. rw 0 0.10 isolate 1 = electrical isolation of phy from mii /rmii 0 = normal operation rw set by the iso strapping pin. see the ? strapping options ? ksz8091mnx ? section for details. 0.9 restart auto - negotiation 1 = restart auto - negotiation process 0 = normal operation. this bit is self - cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full - duplex 0 = half - duplex rw the inverse of the duplex strapping pin value. see the ? strapping options ? ksz8091mnx ? section for details. 0.7 collision test 1 = enable col tes t 0 = disable col test rw 0 0.6:0 reserved reserved ro 000_0000 register 1h ? basic status 1.15 100base -t4 1 = t4 capable 0 = not t4 capable ro 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 50 revision 1. 2 address name description mode ( 9 ) default 1.14 100base - tx full - duplex 1 = capable of 100mbps full - duplex 0 = not capable of 100mbps full - duplex ro 1 1.13 100base - tx half - duplex 1 = capable of 100mbps half - duplex 0 = not capable of 100mbps half - duplex ro 1 1.12 10base -t full - duplex 1 = capable of 10mbps full - duplex 0 = not capable of 10mbps full - duplex ro 1 1.11 10base -t half - duplex 1 = capable of 10mbps half - duplex 0 = not capable of 10mbps half - duplex ro 1 1.10:7 reserved reserved ro 000_0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto - negotiation complete 1 = auto - negotiation process completed 0 = auto - negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto - negotiation ability 1 = can perform auto - negotiation 0 = cannot perform auto - negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capability registers ro 1 register 2h ? phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the o rganizationally unique identifier (oui). kendin communication?s oui is 0010a1 (hex). ro 0022h register 3h ? phy identifier 2 3.15:10 phy id number assigned to the 19th through 24th bits of the organizationally unique identifier (oui). kendin communicatio n?s oui is 0010a1 (hex). ro 0001_01 3.9:4 model number six - bit manufacturer?s model number ro 01_0110 3.3:0 revision number four - bit manufacturer?s revision number ro indicates silicon revision register 4h ? auto - negotiation advertisement 4.15 next pag e 1 = next page capable 0 = no next page capability rw 0 4.14 reserved reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 51 revision 1. 2 address name description mode ( 9 ) default 4.12 reserved reserved ro 0 4.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetri c pause [11] = asymmetric and symmetric pause rw 00 4.9 100base -t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability rw set by the speed strapping pin (ksz8091rnb onl y) . see the ? strapping options ? ksz8091rnb ? section for details. 4.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability rw set by the speed strapping pin (ksz8091rnb only ). see the ? strapping options ? ksz8091rnb ? section for details. 4.6 10base -t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability rw 1 4.5 10base -t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 register 5h ? auto - negotiation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetric pause ro 00 5.9 100base -t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability ro 0 5.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability ro 0 5.6 10base -t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability ro 0 5.5 10base -t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability ro 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 52 revision 1. 2 address name description mode ( 9 ) default 5.4:0 sel ector field [00001] = ieee 802.3 ro 0_0001 register 6h ? auto - negotiation expansion 6.15:5 reserved reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6. 3 link partner next page able 1 = link partner has next page capability 0 = link p artner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 pa ge received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto - negotiation able 1 = link partner has auto - negotiation capability 0 = link partner d oes not have auto - negotiation capability ro 0 register 7h ? auto - negotiation next page 7.15 next page 1 = additional next pages will follow 0 = last page rw 0 7.14 reserved reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous valu e of the transmitted link code word equaled logic 1 0 = logic 0 ro 0 7.10:0 message field 11- bit wide field to encode 2048 messages rw 000_0000_0001 register 8h ? auto - negotiation link partner next page ability 8.15 next page 1 = additional next pages will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = can act o n the information 0 = cannot act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic 0 0 = previous value of transmitted link code word equal to logic 1 ro 0 8.10:0 message field 11- bit wide field to encode 2048 messages ro 000_0000_0000
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 53 revision 1. 2 address name description mode ( 9 ) default register dh ? mmd access ? control d.15:14 mmd ? operation mode for the selected mmd device address (bits [4:0] of this register), these two bits select one of the following register or data operations and the usage for mmd access ? register/data (reg. eh). 00 = register 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only rw 00 d.13:5 reserved reserved rw 00_0000_000 d.4:0 mmd ? device address these five bits set the mmd device address. rw 0_0000 register eh ? mmd access ? register/data e.15:0 mmd ? register/data for the selected mmd device address (reg. dh, bits [4:0]), when reg. dh, bits [15:14] = 00, this register contains the read/write register ad dress for the mmd device address . otherwise, this register contains the read/write data value for the mmd device address and its selected register address. see also reg. dh, bits [15:14], for descriptions of post increment reads and writes of this register for data operation. rw 0000_0000_0000_0000 note: 9. rw = read/write. ro = read only. sc = self - cleared. lh = latch high. ll = latch low.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 54 revision 1. 2 vendor - specific registers ? descriptions address name description mode ( 10 ) default register 10h ? digital reserved control 10.15:5 reserved reserved rw 0000_0000_000 10.4 pll off 1 = turn pll off automatically in edpd mode 0 = keep pll on in edpd mode. see also r egister 18h, bit [11] for edpd mode rw 0 10.3:0 reserved rese rved rw 0000 register 11h ? afe control 1 11.15:6 reserved reserved rw 0000_0000_00 11.5 slow - oscillator mode enable slow - oscillator mode is used to disconnect the input reference crystal/clock on the xi pin and select the on - chip slow oscillator when t he ksz80 9 1mnx/rnb device is not in use after power -up. 1 = enable 0 = disable this bit automatically sets software power - down to the analog side when enabled. rw 0 11.4:0 reserved reserved rw 0_0000 register 13 h ? afe control 4 13 .15: 5 reserved reserved rw 0000_ 000 0 _000 13. 4 10base - te mode 1 = eee 10base - te (1.75v tx amplitude) 0 = standard 10base - t (2.5v tx amplitude) rw 0 13.3:0 reserved reserved rw 0000 register 15h ? rxer counter 15.15:0 rxer counter receive error counter for symbol error frames ro/sc 0000h register 16h ? operation mode strap override 16.15 pme enable pme for wake -on- lan 1 = enable 0 = disable this bit works i n conjunction with mmd address 1fh, reg. 0h, bits [15:14] to define the output f or pins 21 and 30. rw set by the pme_en strapping pin. see the ? strapping options ? ksz8091mnx ? section for details. 16.14 :11 reserved reserved rw 000_0 16.10 reserved reserved ro 0 16.9 b- cast_off override 1 = override strap - in for b - cast_off if bit is ?1?, phy address 0 is non - broadcast. rw 0 16.8 reserved reserved rw 0 16.7 mii b -to -b override 1 = override strap - in for mii back -to - back mode (also set bit 0 of this register to ?1?) this bit applies only to ksz80 9 1mnx. rw 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 55 revision 1. 2 address name description mode ( 10 ) default 16.6 rmii b -to -b overr ide 1 = override strap - in for rmii back -to - back mode (also set bit 1 of this register to ?1?) this bit applies only to ksz80 9 1rnb. rw 0 16.5 nand tree override 1 = override strap - in for nand tree mode rw 0 16.4:2 reserved reserved rw 0_00 16.1 rmii ove rride 1 = override strap - in for rmii mode this bit applies only to ksz80 9 1rnb. rw 0 16.0 mii override 1 = override strap - in for mii mode this bit applies only to ksz80 9 1mnx. rw 1 register 17h ? operation mode strap status 17.15:13 phyad[2:0] strap - in st atus [000] = strap to phy address 0 [001] = strap to phy address 1 [010] = strap to phy address 2 [011] = strap to phy address 3 [100] = strap to phy address 4 [101] = strap to phy address 5 [110] = strap to phy address 6 [111] = strap to phy address 7 ro 17.12:10 reserved reserved ro 17.9 b- cast_off strap - in status 1 = strap to b - cast_off if bit is ?1?, phy address 0 is non - broadcast. ro 17.8 reserved reserved ro 17.7 mii b -to -b strap - in status 1 = strap to mii back -to - back mode this bit applies on ly to ksz80 9 1mnx. ro 17.6 rmii b -to -b strap - in status 1 = strap to rmii back - to - back mode this bit applies only to ksz80 9 1rnb. ro 17.5 nand tree strap - in status 1 = strap to nand tree mode ro 17.4:2 reserved reserved ro 17.1 rmii strap - in status 1 = strap to rmii mode this bit applies only to ksz80 9 1rnb. ro 17.0 mii strap - in status 1 = strap to mii mode this bit applies only to ksz80 9 1mnx. ro register 18h ? expanded control 18.15:12 reserved reserved rw 0000 18.11 edpd disabled energy - detect p ower - down mode 1 = disable 0 = enable see also r egister 10h, bit [4] for pll off. rw 1
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 56 revision 1. 2 address name description mode ( 10 ) default 18.10 100base - tx latency 1 = mii output is random latency 0 = mii output is fixed latency for both settings, all bytes of received preamble are passed to the mii output . this bit applies only to the ksz80 9 1mnx. rw 0 18.9:7 reserved reserved rw 00_0 18.6 10base -t preamble restore 1 = restore received preamble to mii output 0 = remove all seven bytes of preamble before sending fr ame (starting with sfd) to mii output this bit applies only to the ksz80 9 1mnx . rw 0 18.5:0 reserved reserved rw 00_000 1 register 1bh ? interrupt control/status 1b.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = e nable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detec t fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = di sable link partner acknowledge interrupt rw 0 1b.10 link - down interrupt enable 1= enabl e link - down interrupt 0 = disable link - down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link - up interrupt enable 1 = enable link - up interrupt 0 = disable link - up interru pt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occur ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occur ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occur ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occur ro/sc 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 57 revision 1. 2 address name description mode ( 10 ) default 1b.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occur ro/sc 0 1b.2 link - down interrupt 1 = link - down occurred 0 = link - down did not occur ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occur ro/sc 0 1b.0 link - up interrupt 1 = link - up occurred 0 = link - up did no t occur ro/sc 0 register 1dh ? linkmd c able diagnostic 1d.15 cable diagnostic test enable 1 = enable cab le diagnostic test. after test has completed, this bit is self - cleared. 0 = indicates cabl e diagnostic test (if enabled) has comple ted and the status information is valid for read. rw/sc 0 1d.14:13 cable diagnostic test result [00] = normal condition [01] = open condition has been detected in c able [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12 short cable indicator 1 = short cable (<10 meter) has been detected by linkmd ro 0 1d.11:9 reserved reserved rw 000 1d.8:0 cable fault counter distance to fault ro 0_0000_0000 register 1eh ? phy control 1 1e.15:10 reserved reserved ro 0000_00 1e.9 ena ble pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 1e.8 link status 1 = link is up 0 = link is down ro 0 1e.7 polarity status 1 = polarity is reversed 0 = polarity is not reversed ro 1e.6 reserved reserved ro 0 1e.5 mdi/mdi - x state 1 = mdi - x 0 = mdi ro 1e.4 energy detect 1 = signal p resent on receive differential pair 0 = no signal de tected on receive differential pair ro 0 1e.3 phy isolate 1 = phy in isolate mode 0 = phy in normal operation rw 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 58 revision 1. 2 address name description mode ( 10 ) default 1e.2:0 operation mode indication [000] = still in auto - negotiation [001] = 10base - t half - duplex [010] = 100base - tx half - duplex [011] = reserved [100] = reserved [101] = 10base - t full - duplex [110] = 100base - tx full - duplex [111] = reserved ro 000 register 1fh ? phy control 2 1f.15 hp_mdix 1 = hp auto mdi/mdi - x mode 0 = micrel auto mdi/mdi - x mode rw 1 1f.14 mdi/mdi - x select when auto mdi/mdi - x is disabled, 1 = mdi - x mode trans mit on rxp,rxm (pins 5, 4) and receive on txp,txm (pins 7, 6) 0 = mdi mode tran smit on txp,txm (pin s 7, 6) and receive on rxp,rxm (pins 5, 4) rw 0 1f.13 pair swap disable 1 = disable auto mdi/mdi - x 0 = enable auto mdi/mdi - x rw 0 1f.12 reserved reserved rw 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control l ogic and allows the transmitter to send a pattern even if there is no link. rw 0 1f.10 power saving 1 = enable power saving 0 = disable power saving rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable j abber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7 rmii reference clock select 1 = rmii 50mhz clock mode; clock input to xi (pin 9) is 50mhz 0 = rmii 25mhz clock mode; clock input to xi (pin 9) is 25mhz this bit applies only to ksz80 9 1r nb. rw 0 1f.6 reserved reserved rw 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 59 revision 1. 2 address name description mode ( 10 ) default 1f.5:4 led mode [00] = led1: speed led0: link/activity [01] = led1: activity led0: link [10], [11] = reserved the led1 pin applies only to the ksz8091rnb. rw 00 1f.3 disable transmitter 1 = disable transmitter 0 = enable transmitter rw 0 1f.2 remote loopback 1 = remote (analog) loopback is enabled 0 = normal mode rw 0 1f.1 enable sqe test 1 = enable sqe test 0 = disable sqe test rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 note: 10. rw = read/write. ro = read only. sc = self - cleared.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 60 revision 1. 2 mmd r egister s mmd registers provide indirect read/write access to up to 32 mmd device addresses with each device supporting up to 65,536 16 - bit registers, as defined in clause 22 of the ieee 802.3 specification. the ksz8091mnx/rnb , however, uses only a small fraction of the available registers. see the ? register map ? section for a list of supported mmd device addresses and their associated register addresse s. the following two standard registers serve as the portal registers to access the indirect mmd registers. ? standard r egister dh ? mmd access ? control ? standard r egister eh ? mmd access ? register/data table 15 . portal registers (a ccess to indirect mmd registers) address name description mode default register dh ? mmd access ? control d.15:14 mmd ? operation mode for the selected mmd device address (bits [4:0] of this register), these two bits select one of the following registe r or data operations and the usage for mmd access ? register/data (reg. eh). 00 = register 01 = data, no post increment 10 = data, post increment on reads and writes 11 = data, post increment on writes only rw 00 d.13:5 reserved reserved rw 00_0000_000 d.4:0 mmd ? device address these five bits set the mmd device address. rw 0_0000 register eh ? mmd access ? register/data e.15:0 mmd ? register/data for the selected mmd device address (reg. dh, bits [4:0]), when reg. dh, bits [15:14] = 00, this regi ster contains the read/write register address for the mmd device address. otherwise, this register contains the read/write data value for the mmd device address and its selected register address. see also register dh, bits [15:14] descriptions for post inc rement reads and writes of this register for data operation. rw 0000_0000_0000_0000 examples: mmd register write write mmd ? device address 1fh, register 0h = 0001h to enable link - up detection to trigger pme for wol. 1. write r egister dh with 001fh // set u p register address for mmd ? device address 1fh. 2. write r egister eh with 0000h // select register 0h of mmd ? device address 1fh. 3. write r egister dh with 401fh // select register data for mmd ? device address 1fh, register 0h. 4. writ e r egister eh with 0001h // write value 0001h to mmd ? device address 1fh, register 0h.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 61 revision 1. 2 mmd register read read mmd ? device address 1fh, register 19h ? 1bh for the magic packet?s mac address 1. write r egister dh with 001fh // set up register address for mmd ? device address 1fh. 2. write r egister eh with 0019h // select r egister 19h of mmd ? device address 1fh. 3. write r egister dh with 801fh // select register data for mmd ? device address 1fh, register 19h // with post increments 4. read r egister eh // read data in mmd ? device address 1fh, register 19h. 5. read r egister eh // read data in mmd ? device address 1fh, register 1ah. 6. read r egister eh // read data in mmd ? device address 1fh, register 1bh. mmd registers ? descriptions address name description mode ( 11 ) default mmd address 1 h, register 0 h ? pma/pmd control 1 1. 0.15 :13 reserved reserved rw 000 1.0.12 lpi enable lower power idle enable rw 0 1. 0. 11:0 reserved reserved rw 0000_0000_0000 mmd address 1h, register 1 h ? pma/pmd status 1 1.1 .15 :9 reserved reserved ro 0000_000 1.1.8 lpi state entered 1 = pma/pmd has entered lpi state 0 = pma/pmd has not entered lpi state ro/lh 0 1.1.7:4 reserved reserved ro 0000 1.1.3 lpi state indication 1 = pma/pmd is currently in lpi state 0 = pma /pmd is currently not in lpi state ro 0 1.1.2:0 reserved reserved ro 000 mmd address 3h, re gister 0 h ? eee pcs control 1 3.0.15:12 reserved reserved ro 0000 3.0.11 reserved reserved rw 1 3.0.10 100base - tx rxc clock stoppable during receive lower - power idle mode, 1 = rxc clock is stoppable for 100base -tx 0 = rxc clock is not stoppable for 100base -tx this bit applies only to ksz80 91mnx . rw 1 3.0.9:4 reserved reserved rw 00_0001 3.0.3:2 reserved reserved ro 00 3.0.1:0 reserved reserved rw 00 mmd addr ess 7h, re gister 3c h ? eee advertisement 7.3c.15:3 reserved reserved ro 0000_0000_0000_0 7.3c.2 1000base -t eee capable 0 = 1000mbps eee is not supported ro 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 62 revision 1. 2 address name description mode ( 11 ) default 7.3c.1 100base - tx eee capable 1 = 100mbps eee capable 0 = no 100mbps eee capability this bit is set to ?0? as the default after power -up or reset. set this bit to ?1? to enable 100mbps eee mode. rw 0 7.3c.0 reserved reserved ro 0 mmd address 7h, register 3d h ? eee link partner advertisement 7.3d.15:3 reserved reserved ro 0000_0000_0000_0 7.3d.2 1000base -t eee capable 1 = 1000mbps eee capable 0 = no 1000mbps eee capability ro 0 7.3d.1 100base - tx eee capable 1 = 100mbps eee capable 0 = no 100mbps eee capability ro 0 7.3d.0 reserved reserved ro 0 mmd address 1fh, re gister 0 h ? wake - on - lan ? contr ol 1f.0.15:14 pme output select these two bits work in conjunction with reg. 16 h, bit [15] for pme enable to define the output for pins 21 and 30 . intrp/pme_n2 (pin 21) 00 = intrp output 01 = pme_n2 output 10 = intrp and pme_n2 output 11 = reserved le d0/pme_n1 (pin 30) 00 = pme_n1 output 01 = led0 output 10 = led0 output 11 = pme_n1 output rw 00 1f.0.13:7 reserved reserved ro 00_0000_0 1f.0.6 magic packet detect enable 1 = enable magic - packet detection 0 = disable magic - packet detection rw 0 1f. 0.5 custom - packet type 3 detect enable 1 = enable custom - packet, type 3 detection 0 = disable custom - packet, type 3 detection rw 0 1f.0.4 custom - packet type 2 detect enable 1 = enable custom - packet, type 2 detection 0 = disable custom - packet, type 2 detec tion rw 0 1f.0.3 custom - packet type 1 detect enable 1 = enable custom - packet, type 1 detection 0 = disable custom - packet, type 1 detection rw 0 1f.0.2 custom - packet type 0 detect enable 1 = enable custom - packet, type 0 detection 0 = disable custom - packet , type 0 detection rw 0 1f.0.1 link - down detect enable 1 = enable link - down detection 0 = disable link - down detection rw 0
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 63 revision 1. 2 address name description mode ( 11 ) default 1f.0.0 link - up detect enable 1 = enable link - up detection 0 = disable link - up detection rw 0 mmd address 1fh, register 1 h ? wake -o n - lan ? customized packet, type 0, mask 0 mmd address 1fh, register 7 h ? wake - on - lan ? customized packet, type 1, mask 0 mmd address 1fh, register d h ? wake - on - lan ? customized packet, type 2, mask 0 mmd address 1fh, register 13 h ? wake - on - lan ? customized packet, type 3, mask 0 1f.1.15:0 1f.7.15:0 1f.d.15:0 1f.13.15:0 custom packet type x mask 0 this register selects the bytes in the first 16 bytes of the packet (bytes 1 thru 16) that will be used for crc calculation. for each bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register - bit to packet - byte mapping is as follows: bit [15] : byte -16 ? : ? bit [1] : byte -2 bit [0] : byte -1 rw 0000_0000_0000_0000 mmd address 1fh, register 2 h ? wake - on - lan ? customized packet, type 0, mask 1 mmd address 1fh, register 8 h ? wake - on - lan ? customized packet, type 1, mask 1 mmd address 1fh, register e h ? wake - on - lan ? customized packet, type 2, mask 1 mmd address 1fh, register 14 h ? wake - on - lan ? customiz ed packet, type 3, mask 1 1f.2.15:0 1f.8.15:0 1f.e.15:0 1f.14.15:0 custom packet type x mask 1 this register selects the bytes in the second 16 bytes of the packet (bytes 17 thru 32) that will be used for crc calculation. for each bit in this registe r, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register - bit to packet - byte mapping is as follows: bit [15] : byte -32 ? : ? bit [1] : byte -18 bit [0] : byte -17 rw 0000_0000_0000_0000
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 64 revision 1. 2 address name description mode ( 11 ) default mmd address 1fh, register 3 h ? wake - on - lan ? customized packet, type 0, mask 2 mmd address 1fh, register 9 h ? wake - on - lan ? customized packet, type 1, mask 2 mmd address 1fh, register f h ? wake - on - lan ? customized packet, type 2, mask 2 mmd address 1fh, register 15 h ? wake - on - lan ? customized packet, type 3, mask 2 1f.3.15:0 1f.9.15:0 1f.f.15:0 1f.15.15:0 custom packet type x mask 2 this register selects the bytes in the third 16 bytes of the packet (bytes 33 thru 48) that will be used for crc calculation. for each bit in thi s register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register - bit to packet - byte mapping is as follows: bit [15] : byte -48 ? : ? bit [1] : byte -34 bit [0] : byte -33 rw 0000_0000_0000_0000 mmd address 1fh, register 4 h ? wake - on - lan ? customized packet, type 0, mask 3 mmd address 1fh, register a h ? wake - on - lan ? customized packet, type 1, mask 3 mmd address 1fh, register 10 h ? wake - on - lan ? customized packet, type 2, mask 3 mmd address 1fh, register 16 h ? wa ke- on - lan ? customized packet, type 3, mask 3 1f.4.15:0 1f.a.15:0 1f.10.15:0 1f.16.15:0 custom packet type x mask 3 this register selects the bytes in the fourth 16 bytes of the packet (bytes 49 thru 64) that will be used for crc calculation. for eac h bit in this register, 1 = byte is selected for crc calculation 0 = byte is not selected for crc calculation the register - bit to packet - byte mapping is as follows: bit [15] : byte -64 ? : ? bit [1] : byte -50 bit [0] : byte -49 rw 0000_0000_0000_0000 mmd address 1fh, register 5 h ? wake - on - lan ? customized packet, type 0, expected crc 0 mmd address 1fh, register b h ? wake - on - lan ? customized packet, type 1, expected crc 0 mmd address 1fh, register 11 h ? wake - on - lan ? customized packet, type 2, expected crc 0 mmd address 1fh, register 17 h ? wake - on - lan ? customized packet, type 3, expected crc 0 1f.5.15:0 1f.b.15:0 1f.11.15:0 1f.17.15:0 custom packet type x crc 0 this register stores the lower two bytes for the expected crc. bit [15:8] = byte 2 (crc [15:8 ]) bit [7:0] = byte 1 (crc [7:0]) the upper two bytes for the expected crc are stored in the following register. rw 0000_0000_0000_0000
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 65 revision 1. 2 address name description mode ( 11 ) default mmd address 1fh, register 6 h ? wake - on - lan ? customized packet, type 0, expected crc 1 mmd address 1fh, register c h ? wake - on - lan ? customized packet, type 1, expected crc 1 mmd address 1fh, register 12 h ? wake - on - lan ? customized packet, type 2, expected crc 1 mmd address 1fh, register 18 h ? wake - on - lan ? customized packet, type 3, expected crc 1 1f.6.15:0 1f.c.15:0 1f .12.15:0 1f.18.15:0 custom packet type x crc 1 this register stores the upper two bytes for the expected crc. bit [15:8] = byte 4 (crc [31:24]) bit [7:0] = byte 3 (crc [23:16]) the lower two bytes for the expected crc are stored in the previous r egister. rw 0000_0000_0000_0000 mmd address 1fh, register 19 h ? wake - on - lan ? magic packet, mac -da -0 1f.19.15:0 magic packet mac -da -0 this register stores the lower two bytes of the destination mac address for the magic packet. bit [15:8] = byte 2 (m ac address [15:8]) bit [7:0] = byte 1 (mac address [7:0]) the upper four bytes of the destination mac address are stored in the following two registers. rw 0000_0000_0000_0000 mmd address 1fh, register 1a h ? wake - on - lan ? magic packet, mac -da -1 1f.1a.1 5:0 magic packet mac -da -1 this register stores the middle two bytes of the destination mac address for the magic packet. bit [15:8] = byte 4 (mac address [31:24]) bit [7:0] = byte 3 (mac address [23:16]) the lower two bytes and upper two bytes of the destination mac address are stored in the previous and following registers, respectively. rw 0000_0000_0000_0000 mmd address 1fh, register 1b h ? wake - on - lan ? magic packet, mac - da - 2 1f.1b.15:0 magic packet mac -da -2 this register stores the upper two b ytes of the destination mac address for the magic packet. bit [15:8] = byte 6 (mac address [47:40]) bit [7:0] = byte 5 (mac address [39:32]) the lower four bytes of the destination mac address are stored in the previous two registers. rw 0000_0000_0000 _0000 note: 11. rw = read/write. ro = read only. lh = latch high.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 66 revision 1. 2 absolute maximum ratings ( 12 ) supply voltage (v in ) (v dd_1.2 ) .................................................. ? 0.5v to +1.8v (v ddio, v dda_3.3 ) ....................................... ? 0.5v to +5.0v input voltage (all inputs) .............................. ? 0.5v to +5.0v output voltage (all outputs) ......................... ? 0.5v to +5.0v lead temperature (soldering, 10s) ............................ 260c storage temperature (t s ) ......................... ? 55c to +150c operating ratings ( 13 ) supply voltage (v ddio_3.3, v dda_3.3 ) .......................... +3.135v to +3.465v (v ddio_2.5 ) ........................................ +2.375v to +2.625v (v ddio_1.8 ) ........................................ +1.710v to +1.890v ambient temperature (t a , commercial) ...................................... 0c to +70c (t a , industrial) ....................................... ? 40c to +85c maximum junction temperature (t j max.) ................ 125c thermal resistance ( ja ) ......................................... 34c/w thermal resistance ( jc ) ........................................... 6c/w electrical characteristics ( 14) symbol parameter condition min . typ . max . units supply current (v ddio , v dda_3.3 = 3.3v) ( 15 ) i dd1_3.3v 10base -t full - duplex traffic @ 100% utilization 41 ma i dd2_3.3v 100base -tx full - duplex traffic @ 100% utilization 47 ma i dd3 _3.3v eee (100mbps) mode tx and rx paths in lpi state with no traffic 23 ma i dd4 _3.3v edpd mode ethernet cabl e disconnected (r eg. 18h.11 = 0) 20 ma i dd5 _3.3v power - down mode software power - down (r eg. 0h.11 = 1) 4 ma cmos level inputs v ih input high voltage v ddio = 3.3v 2.0 v v ddio = 2.5v 1.8 v v ddio = 1.8v 1.3 v v il input low voltage v ddio = 3 .3v 0.8 v v ddio = 2.5v 0.7 v v ddio = 1.8v 0.5 v |i in | input current v in = gnd ~ vddio 10 a cmos level outputs v oh output high voltage v ddio = 3.3v 2.4 v v ddio = 2.5v 2.0 v v ddio = 1.8v 1.5 v v ol output low voltage v ddio = 3.3 v 0.4 v v ddio = 2.5v 0.4 v v ddio = 1.8v 0.3 v |i oz | output tri - state leakage 10 a led output i led output drive current each led pin (led0, led1) 8 ma notes: 12. exceeding the absolute maximum ratings may damage the device. stresses great er than the absolute maximum rating can cause permanent damage to the device. operation of the device at these or any other conditions above those specified in the operating section s of this specification is not implied. maximum conditions for extended per iods may affect reliability. 13. the device is not guaranteed to function outside its operating ratings. 14. t a = 25 c. specification for packaged product only. 15. current consumption is for the single 3.3v supply ksz80 9 1mnx/rnb device only, and includes the transmit driver current and the 1.2v supply voltage (v dd_1.2 ) that are supplied by the ksz80 9 1mnx/rnb.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 67 revision 1. 2 symbol parameter condition min . typ . max . units all pull - up/pull- down pins (including strapping pins) pu internal pull - up resistance v ddio = 3.3v 30 45 73 k v ddio = 2.5v 39 61 102 k v ddio = 1.8v 48 99 178 k pd internal pull - down resistance v ddio = 3.3v 26 43 79 k v ddio = 2.5v 34 59 113 k v ddio = 1.8v 53 99 200 k 100base - tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % output jitter peak -to - peak 0.7 ns 10base - t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 termination across differential output 2.2 2.8 v jitter added peak -to - peak 3.5 ns t r , t f rise/fall time 25 ns 10bas e - t receive v sq squelch threshold 5mhz square wave 400 mv transmitter ? drive setting v set reference voltage of i set r(i set ) = 6.49k 0.65 v ref_clk output 50mhz rmii clock output jitter peak -to - peak (applies only to ksz8091rnb in rmii ? 25mhz cl ock mode) 300 ps 100mbps mode ? industrial applications parameters clock phase delay ? xi input to mii txc output xi (25mhz clock input) to mii txc (25mhz clock output) delay, referenced to rising edges of both clocks. (applies only to ksz80 9 1mnx in m ii mode) 15 20 25 ns t llr link loss reaction (indication) time link loss detected at receive differential inputs to phy signal indication time for each of the following: 1. for led mode 00 (ksz8091rnb only) , speed led output changes from low (100mbps) to high (10mbps, default state for link - down). 2. for led mode 01, link led output changes from low (link - up) to high (link - down). 3. intrp pin asserts for link - down status change. 4.4 s
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 68 revision 1. 2 timing diagrams mii sqe timing (10base - t) figure 16 . mii sqe timing (10base - t) table 16 . mii sqe timing (10base - t) parameters timing parameter description min. typ. max. unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t sqe col (sqe) delay after txen de - asserted 2.2 s t sqep col (sqe) pulse duration 1.0 s
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 69 revision 1. 2 mii transmit timing (10base - t) figure 17 . mii transmit timing (10base - t) table 17 . mii transmit ti ming (10base- t) parameters timing parameter description min. typ. max. unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t su1 txd[3:0] setup to rising edge of txc 120 ns t su2 txen setup to rising edge of txc 120 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 600 ns t crs2 txen low to crs de - asserted latency 1.0 s
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 70 revision 1. 2 mii receive timing (10base - t) figure 18 . mii receive timing (10base - t) table 18 . mii receive timing (10base- t) parameters timing parameter description min. typ. max. unit t p rxc period 400 ns t wl rxc pulse width low 200 ns t wh rxc pu lse width high 200 ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 205 ns t rlat crs to (rxdv, rxd[3:0]) latency 7.2 s
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 71 revision 1. 2 mii transmit timing (100base - tx) figure 19 . mii transmit timing (100base - tx) table 19 . mii transmit timing (100base- tx) parameters timing parameter description min. typ. max. unit t p txc period 40 ns t wl txc pulse width low 20 ns t wh txc pulse width high 20 ns t su1 txd[3:0] setup to rising edge o f txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 72 ns t crs2 txen low to crs de - asserted latency 72 ns
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 72 revision 1. 2 mii receive timing (100base - tx) figure 20 . mii receive timing (100base - tx) table 20 . mii receive timing (100base- tx) parameters timing parameter description min. typ. max. unit t p rxc period 4 0 ns t wl rxc pulse width low 20 ns t wh rxc pulse width high 20 ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 16 2 1 25 ns t rlat crs to (rxdv, rxd[3:0]) latency 170 n s
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 73 revision 1. 2 rmii timing figure 21 . rm ii timing ? data received from rmii figure 22 . rmii timing ? data input to rmii table 21 . rmii timing parameters ? ksz80 9 1rnb (25mhz input to xi pin, 50mhz output from ref_clk pin) timing parameter de scription min. typ. max. unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 7 10 13 ns table 22 . rmii timing parameters ? ksz80 9 1rnb (50mhz input to xi pin) timing parameter description mi n. typ. max. unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 8 11 13 ns
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 74 revision 1. 2 auto - negotiation timing figure 23 . auto - negotiation fast link pulse (flp) timing table 23 . auto - negotiation fast link pulse (flp) timing parameters timing parameter description min. typ. max. unit t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55. 5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulses per flp burst 17 33
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 75 revision 1. 2 mdc/mdio timing figure 24 . mdc/mdio timing table 24 . mdc/mdio timing parameters timi ng parameter description min. typ. max. unit fc mdc clock frequency 2.5 10 mhz t p mdc period 400 ns t md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay fro m rising edge of mdc 5 222 ns
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 76 revision 1. 2 power - up/reset timing the ksz80 9 1mnx/rnb reset timing requirement is summarized in figure 25 and table 25 . figure 25 . power - up/reset timing table 25 . power - up/reset timing parameters timing parameter description min. typ. max. unit t vr supply voltage (v ddio, v dda_3.3 ) rise time 300 s t sr stable supply voltage (v ddio, v dda_3.3 ) to re set high 10 ms t cs configuration setup time 5 ns t ch configuration hold time 5 ns t rc reset to strap - in pin output 6 ns the supply voltage ( v ddio and v dda_3.3 ) power - up waveform should be monotonic. the 300 s minimum rise time is from 10% to 9 0%. for warm reset, the reset (rst#) pin should be asserted low for a minimum of 500 s. the strap - in pin values are read and updated at the de - assertion of reset. after the de - assertion of reset, wait a minimum of 100 s before starting programming on the m iim (mdc/mdio) interface.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 77 revision 1. 2 reset circuit figure 26 shows a reset circuit recommended for powering up the ksz80 9 1mnx/rnb if reset is triggered by the power supply. figure 26 . recommende d reset circuit figure 27 s hows a reset circuit recommended for applications where reset is driven by another device (for example, the cpu or an fpga). the reset out rst_out_n from cpu/fpga provides the warm rese t after power up reset . d2 is used if using different vddio between the switch and cpu/fpga, otherwise, the different vddio will fight each other. if different vddio have to use in a special case, a low vf (<0.3v) diode is required (for example, vishay?s b at54, mss1p2l and so on), or a level shifter device can be used too. if ethernet device and cpu/fpga use same vddio voltage, d2 can be removed to connect both devices directly. usually, ethernet device and cpu/fpga should use same vddio voltage. figure 27 . recommended reset circuit for interfacing with cpu/fpga reset output
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 78 revision 1. 2 reference circuits ? led strap- in pins the pull - up, float, and pull - down reference circuits for the led1/speed and led0 /pme_n1 /nwayen strapping pins are sh own in figure 28 for 3.3v and 2.5v vddio. figure 28 . reference circuits for led strapping pins for 1.8v vddio, led indication support is not recommended due to the low voltage. without the led indicator, the speed and nwayen strapping pins are functional with a 4.7k pull - up to 1.8v vddio or float for a value of ?1?, and with a 1.0k pull - down to ground for a value of ?0?. note: if using rj45 j acks with integrated leds and 1.8v vddio, a level shifting is required from led 3.3v to 1.8v. for example, use a bipolar tran sistor or a level shift device.
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 79 revision 1. 2 reference clock ? connection and selection a crystal or external clock source, such as an oscillator, is used to provide the reference clock for the ksz80 9 1mnx/rnb. for the ksz80 9 1mnx in all operating modes and for the ksz8 0 9 1rnb in rmii ? 25mhz clock mode, the reference clock is 25 mhz. the reference clock connections to xi (pin 9) and xo (pin 8 ), and the reference clock selection criteria, are provided in figure 29 and table 26 . figure 29 . 25mhz crystal/oscillator reference clock connection table 26 . 25mhz crys tal/ reference clock selection criteria characteristics value units frequency 2 5 mhz frequency tolerance (max.) () 50 ppm crystal series resistance (typ.) 40 crystal load capacitance (typ.) 22 pf note: 16. 60ppm for over temperature crystal. for the ksz80 9 1rnb in rmii ? 50mhz clock mode, the reference clock is 50mhz. the reference clock connections to xi (pin 9), and the reference clock selection criteria a re provided in figure 30 and table 27 . figure 30 . 50mhz oscillator reference clock connection table 27 . 50mhz oscilla tor /reference clock selection criteria characteristics value units frequency 50 mhz frequency tolerance (max.) 50 ppm
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 80 revision 1. 2 magnetic ? connection and selection a 1:1 isolation transformer is required at the line interface. use one with integrated common - mode chokes for designs exceeding fcc requirements. the ksz80 9 1mnx/rnb design incorporates voltage - mode transmit drivers and on - chip terminations. with the voltage - mode implementation, the transmit drivers supply the common - mode voltages to the two different ial pairs. therefore, the two transformer center tap pins on the ksz80 9 1mnx/rnb side should not be connected to any power supply source on the board; instead, the center tap pins should be separated from one another and connected through separate 0.1f common - mode capacitors to ground. separation is required because the common - mode voltage is different between transmitting and receiving differential pairs . figure 31 shows the typical magnetic interface circuit for the ksz80 9 1mnx/rnb. figure 31 . typical magnetic interface circuit
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 81 revision 1. 2 table 28 lists recommended magnetic char acteristics. table 28 . magnetics selection criteria parameter value test condition turns ratio 1 ct : 1 ct open - circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss (typ.) ? 1.1db 100khz to 100mhz hipot (min.) 1500 vrms table 29 is a list of compatible single - port magnetics with separated transformer center tap pins on the phy chip side that can be used with the ksz80 9 1mnx/rnb. table 29 . compatible single - port 10/100 magnetics manufacturer part number temperature range magnetic + rj -45 bel fuse s558 - 5999-u7 0c to 70c no bel fuse si - 46001-f 0c to 70c yes bel fuse si - 50170-f 0c to 70c yes delta lf8505 0c to 70c no halo hfj11 - 2450e 0c to 70c yes halo tg110 - e055n5 ? 40c to 85c no lankom lf - h41s -1 0c to 70c no pulse h1102 0c to 70c no pulse h1260 0c to 70c no pulse hx1188 ? 40c to 85c no pulse j00 - 0014 0c to 70c yes pulse jx0011d21nl ? 40c to 85c yes tdk tla - 6t718a 0c to 70c yes transpower hb726 0c to 70c no wurth/midcom 000- 7090- 37r - lf1 ? 40c to 85c no
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 82 revision 1. 2 package information and recommended land pattern ( 17) 32- pin (5mm x 5mm) qfn note: 17. package information is corre ct as of the publication date. for updates and most current information, go to www.micrel.com .
micrel, inc. ksz8091mnx/ksz8091rnb august 31 , 2015 83 revision 1. 2 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel, inc. is a leading global manufacturer of ic solutions for the worldwide high performance linear and power, lan, and t iming & communications markets. the company?s products include advanced mixed - sig nal, analog & power semiconductors; high - performance communication, clock management, mems - based clock oscillators & crystal - less clock generators, ethernet switches, and physical layer transceiver ics. company customers include leading manufacturers of e nterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products. corporation headquarters and state - of - the - art wafer fabrication facilities are located in san jose, ca, with regional sales and support offices and advanced tec hnology design centers situated throughout the americas, europe, and asia. additionally, the company maintains an extensive network of distributors and reps worldwide. micrel makes no representations or warranties with respect to the accuracy or complete ness of the information furnished in this datasheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right t o change circuitry, specifications and descriptions at any time without n otice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, m icrel assumes no liability what soever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including lia bility or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or ot her intellectual property right. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where mal function of a product can reasonably be expected to result in personal injury. life support devic es or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a signific ant injury to the user. a purchaser?s use or sale o f micrel products for use in life support appliances, devices or systems is a purchaser?s own risk and purchaser agrees to fu lly indemnify micrel for any damages resulting from such use or sale . ? 20 13 micrel, incorporated.

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